aP8910A APLUS [Aplus Intergrated Circuits], aP8910A Datasheet - Page 11

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aP8910A

Manufacturer Part Number
aP8910A
Description
Standard CMOS process
Manufacturer
APLUS [Aplus Intergrated Circuits]
Datasheet

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CPU Parallel Trigger Mode
In this mode, S1 to S4 are set to HIGH or LOW according to the table above and followed by
setting the SBT input pin to HIGH, the corresponding Voice Group will be triggered.
Trigger options defined in Fig. 4, 5, 7 and 8 are valid for this mode.
Note that SBT pin cannot be used as Single Button Sequential trigger in this mode. In stead, it
acts as a Strobe input to clock-in the data input from S1 to S4 into the chip.
Voice Groups address is determined by the Voice Group Trigger Table. For example:
Ver 2.1
S1..S4 = 1000 for Voice Group #1
S1..S4 = 0100 for Voice Group #2
S1..S4= 1100 for Voice Group #5
S1..S4 = 1110 for Voice Group #9
S1..S4 = 1101 for Voice Group #12
Integrated Circuits Inc.
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Fig. 11 CPU Parallel Trigger Mode
11
aP8921A/10A
Apr 3, 2007

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