VSC8169QR VITESSE [Vitesse Semiconductor Corporation], VSC8169QR Datasheet

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VSC8169QR

Manufacturer Part Number
VSC8169QR
Description
OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator
Manufacturer
VITESSE [Vitesse Semiconductor Corporation]
Datasheet

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Part Number:
VSC8169QR
Manufacturer:
VITESSE
Quantity:
10
G52230-0, Rev 3.6
01/02/01
Preliminary Data Sheet
VSC8169
Features
General Description
ating at a standard 2.48832Gb/s data rate or a forward error correction (FEC) data rate up to 2.7Gb/s. The inter-
nal clock generator uses a Phase-Locked Loop (PLL) to multiply either a 77.76MHz (up to 84.38MHz-FEC) or
a 155.52MHz (up to 168.75MHz -FEC) reference clock in order to provide the 2.48832GHz (up to 2.7GHz -
FEC) clock for internal logic and output retiming. For use with the VSC9210 FEC Encoder/Decoder chipset
running at 2.654208Gb/s, a reference clock of 82.944MHz (serial rate divided by 32) should be used. The 16-bit
parallel interface incorporates an on-board FIFO eliminating loop timing design issues by providing a flexible
parallel timing architecture. The device operates using a 3.3V power supply, and is packaged in a thermally-
enhanced plastic package. The thermal performance of the 128-pin PQFP allows the use of the VSC8169 with-
out a heat sink under most thermal conditions.
VSC8169 Block Diagram
REFCLKO+
F_FREQSEL
REFCLKO-
• 16:1 Multiplexer Up to 2.7Gb/s
• Targeted for SONET OC-48 / SDH STM-16 (FEC)
• Differential LVPECL Low-Speed Interface
REFCLK+
Applications
The VSC8169 is a 16:1 multiplexer with integrated clock generator for use in SONET/SDH systems oper-
CLK16O+
REFCLK-
CLK16O-
CLK16I+
CLK16I-
Reset
D15+
D15-
D0+
D0-
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
VITESSE
SEMICONDUCTOR CORPORATION
Divide
by 2
Pointer
Pointer
Write
Read
Internet: www.vitesse.com
2.6GHz
PLL
Divide by 16
• On-Chip PLL-Based Clock Generator
• 128-Pin 14x20mm PQFP Package
• Single +3.3V Supply
Control
FIFO
Output
Retime
OC-48 (FEC) 16:1 SONET/SDH
MUX with Clock Generator
FIFO_WAR
CLKO+
CLKO-
DO+
DO-
Page 1

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VSC8169QR Summary of contents

Page 1

Preliminary Data Sheet VSC8169 Features • 16:1 Multiplexer Up to 2.7Gb/s • Targeted for SONET OC-48 / SDH STM-16 (FEC) Applications • Differential LVPECL Low-Speed Interface General Description The VSC8169 is a 16:1 multiplexer with integrated clock generator for use ...

Page 2

OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator Functional Description Low-Speed Interface The Upstream Device should use the CLK16O as the timing source for its final output latch (see Figure 1). The Upstream Device should then generate a CLK16I that ...

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Preliminary Data Sheet VSC8169 PLL locked to reference clock. Minimum 5 CLK16 cycles RESET Holding RESET “low” for a minimum of 5 CLK16 cycles, then setting “high” enables FIFO operation. Holding RESET constantly “low” bypasses the FIFO for transparent mode ...

Page 4

OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator Figure 5: AC Termination of CLK16O+/-, REFCLKO+/- VSC8169 High-Speed Data and Clock Output The high-speed data and clock output drivers consist of a differential pair designed to drive a 50 transmis- sion ...

Page 5

Preliminary Data Sheet VSC8169 The customer can select to provide either a 77.76MHz (up to 84.38MHz- FEC) reference (recommended), or the 2x of that reference, 155.52MHz (up to 168.75MHz-FEC). REF_FREQSEL is used to select the desired reference frequency. REF_FREQSEL = ...

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OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator Supplies The VSC8169 is specified as a LVPECL device with a single positive 3.3V supply. Should the user desire to use the device in an ECL environment with a negative 3.3V supply, ...

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Preliminary Data Sheet VSC8169 AC Characteristics Figure 9: Parallel Input Data and Clock Timing Waveform CLK16I+ Parallel Data Clock Input TXIN[0:15]+, TXPRTYIN Parallel Data Inputs CLK16O+ Parallel Data Clock Output Figure 10: Serial Data and Clock Output Phase Timing Waveform ...

Page 8

OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator Table 1: AC Characteristics Parameters Description Data setup time to the rising t DSU edge of CLK16I+ Data hold time after the rising t DH edge of CLK16 DO± rise ...

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Preliminary Data Sheet VSC8169 Table 2: DC Characteristics Parameters Description V Output HIGH voltage (DO) OH(DO) V Output LOW voltage (DO) OL(DO) Data output differential voltage V OD(DO) (DO) CLK output differential voltage V OCLK(CLKO) (CLKO) V Output common-mode voltage ...

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OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator Figure 12: Parametric Measurement Information PECL Rise and Fall Time T r Absolute Maximum Ratings Power Supply Voltage, (V )..........................................................................................................-0.5V to +3. Input Voltage (Differential inputs)....................................................................................-0. Input ...

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Preliminary Data Sheet VSC8169 Package Pin Descriptions VCC 4 VEEP_CLK 5 VEEP_CLK 6 7 VEEP_CLK 8 VCC 9 CLKO+ CLKO- 10 VCC 11 VCC VEE 15 VEE 16 VEE ...

Page 12

OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator Table 3: Package Pin Identification Pin # Name I — — — 4 VCC — 5 VEEP_CLK — 6 VEEP_CLK — 7 VEEP_CLK — 8 VCC ...

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Preliminary Data Sheet VSC8169 Pin # Name I — — — 38 REF_FREQSEL I 39 VCC — 40 VEE — FIFO_WARN 42 VEE — 43 VCC — 44 RESET ...

Page 14

OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator Pin # Name I/O 69 VEE — VCC — VCC — ...

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Preliminary Data Sheet VSC8169 Pin # Name I/O 104 NC — 105 D14- I 106 D14+ I 107 VCC — 108 D15- I 109 D15+ I 110 VEE — 111 NC — 112 NC — 113 NC — 114 NC ...

Page 16

OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator Package Information PIN 128 PIN 1 EXPOSED INTRUSION 0.127 MAX. EXPOSED HEATSINK PIN 38 10 TYP TYP. Notes: 1) Drawing is not to scale 2) All dimensions ...

Page 17

Preliminary Data Sheet VSC8169 Thermal Considerations This package has been enhanced with a copper heat slug to provide a low thermal resistance path from the die to the exposed surface of the heat spreader. The thermal resistance is shown in ...

Page 18

OC-48 (FEC) 16:1 SONET/SDH MUX with Clock Generator The results of this calculation are listed below: Table 6: Maximum Ambient Air Temperature without Heatsink Airflow Max Ambient Tempeature ( None 100 lfpm 200 lfpm 400 lfpm 600 lfpm Note that ...

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