MAX3000A_06 ALTERA [Altera Corporation], MAX3000A_06 Datasheet

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June 2006, ver. 3.5 ■ Features... ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Table 1. MAX 3000A Device Features Feature EPM3032A Usable gates 600 Macrocells 32 Logic array blocks 2 Maximum user I/O 34 pins t (ns) ...

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MAX 3000A Programmable Logic Device Family Data Sheet ...and More ■ ■ Features ■ ■ ■ ■ ■ ■ ■ ■ ■ General MAX 3000A devices are low–cost, high–performance devices based on the Altera MAX architecture. Fabricated with advanced CMOS ...

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The MAX 3000A architecture supports 100% transistor-to-transistor logic (TTL) emulation and high–density small-scale integration (SSI), medium-scale integration (MSI), and large-scale integration (LSI) logic functions. The MAX 3000A architecture easily integrates multiple devices ranging from PALs, GALs, and 22V10s to MACH ...

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MAX 3000A Programmable Logic Device Family Data Sheet MAX 3000A devices contain 32 to 512 macrocells, combined into groups of 16 macrocells called logic array blocks (LABs). Each macrocell has a programmable–AND/fixed–OR array and a configurable register with independently programmable ...

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Figure 1. MAX 3000A Device Block Diagram INPUT/GCLK1 INPUT/OE2/GCLK2 INPUT/OE1 INPUT/GCLRn Output Enables (1) I/O Control I/O Block I/O Control I/O Block Note: (1) EPM3032A, ...

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MAX 3000A Programmable Logic Device Family Data Sheet Macrocells MAX 3000A macrocells can be individually configured for either sequential or combinatorial logic operation. Macrocells consist of three functional blocks: logic array, product–term select matrix, and programmable register. Figure 2. MAX ...

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For registered functions, each macrocell flipflop can be individually programmed to implement operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; ...

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MAX 3000A Programmable Logic Device Family Data Sheet Expander Product Terms Although most logic functions can be implemented with the five product terms available in each macrocell, highly complex logic functions require additional product terms. Another macrocell can be used ...

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Parallel Expanders Parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. Parallel expanders allow product terms to directly feed the macrocell OR logic, with five product ...

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MAX 3000A Programmable Logic Device Family Data Sheet Figure 4. MAX 3000A Parallel Expanders Unused product terms in a macrocell can be allocated to a neighboring macrocell. 36 Signals 16 Shared from PIA Expanders Programmable Interconnect Array Logic is routed ...

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Figure 5. MAX 3000A PIA Routing While the routing delays of channel–based routing schemes in masked or FPGAs are cumulative, variable, and path–dependent, the MAX 3000A PIA has a predictable delay. The PIA makes a design’s timing performance easy to ...

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MAX 3000A Programmable Logic Device Family Data Sheet Figure 6. I/O Control Block of MAX 3000A Devices PIA Note: (1) EPM3032A, EPM3064A, EPM3128A, and EPM3256A devices have six output enables. EPM3512A devices have 10 output enables. When the tri–state buffer ...

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In–System MAX 3000A devices can be programmed in–system via an industry– standard four–pin IEEE Std. 1149.1-1990 (JTAG) interface. In-system Programma- programmability (ISP) offers quick, efficient iterations during design development and debugging cycles. The MAX 3000A architecture bility internally generates the ...

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MAX 3000A Programmable Logic Device Family Data Sheet Programming Sequence During in-system programming, instructions, addresses, and data are shifted into the MAX 3000A device through the TDI input pin. Data is shifted out through the TDO output pin and compared ...

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By combining the pulse and shift times for each of the programming stages, the program or verify time can be derived as a function of the TCK frequency, the number of devices, and specific target device(s). Because different ISP-capable devices ...

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MAX 3000A Programmable Logic Device Family Data Sheet The programming times described in with the worst-case method using the enhanced ISP algorithm. Table 4. MAX 3000A t & Cycle PULSE Device EPM3032A EPM3064A EPM3128A EPM3256A EPM3512A Tables 5 verification times ...

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Programming MAX 3000A devices can be programmed on Windows–based PCs with an Altera Logic Programmer card, MPU, and the appropriate device adapter. with External The MPU performs continuity checking to ensure adequate electrical contact between the adapter and the device. ...

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MAX 3000A Programmable Logic Device Family Data Sheet The instruction register length of MAX 3000A devices is 10 bits. The IDCODE and USERCODE register length is 32 bits. the boundary–scan register length and device IDCODE information for MAX 3000A devices. ...

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Figure 7 Figure 7. MAX 3000A JTAG Waveforms Captured Table 10 devices. Symbol Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet shows the timing information ...

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MAX 3000A Programmable Logic Device Family Data Sheet Programmable MAX 3000A devices offer a power–saving mode that supports low-power operation across user–defined signal paths or the entire device. This Speed/Power feature allows total power dissipation to be reduced by 50% ...

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Open–Drain Output Option MAX 3000A devices provide an optional open–drain (equivalent to open-collector) output for each I/O pin. This open–drain output enables the device to provide system–level control signals (e.g., interrupt and write enable signals) that can be asserted by ...

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MAX 3000A Programmable Logic Device Family Data Sheet Figure 8. MAX 3000A AC Test Conditions Operating Tables 12 recommended operating conditions, DC operating conditions, and Conditions capacitance for MAX 3000A devices. Table 12. MAX 3000A Device Absolute Maximum Ratings Symbol ...

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Table 13. MAX 3000A Device Recommended Operating Conditions Symbol Parameter V Supply voltage for internal logic and CCINT input buffers V Supply voltage for output drivers, CCIO 3.3–V operation Supply voltage for output drivers, 2.5–V operation V Supply voltage during ...

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MAX 3000A Programmable Logic Device Family Data Sheet Table 15. MAX 3000A Device Capacitance Symbol Parameter C Input pin capacitance IN C I/O pin capacitance I/O Notes to tables: (1) See the Operating Requirements for Altera Devices Data (2) Minimum ...

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Figure 9. Output Drive Characteristics of MAX 3000A Devices Power Because MAX 3000A devices can be used in a mixed–voltage environment, they have been designed specifically to tolerate any possible Sequencing & power–up sequence. The V powered in any order. ...

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MAX 3000A Programmable Logic Device Family Data Sheet Timing Model MAX 3000A device timing can be analyzed with the Altera software, with a variety of popular industry–standard EDA simulators and timing analyzers, or with the timing model shown in devices ...

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Figure 11. MAX 3000A Switching Waveforms t & t < 2 ns. Inputs are R F driven for a logic high and 0 V for a logic low. All timing characteristics are measured at 1.5 V. Shared ...

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MAX 3000A Programmable Logic Device Family Data Sheet Tables 16 EPM3256A, and EPM3512A timing information. Table 16. EPM3032A External Timing Parameters Symbol Parameter t Input to non– PD1 registered output t I/O input to non– PD2 registered output t Global ...

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Table 17. EPM3032A Internal Timing Parameters (Part Symbol Parameter t Input pad and buffer delay IN t I/O input pad and buffer IO delay t Shared expander delay SEXP t Parallel expander delay PEXP t Logic array ...

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MAX 3000A Programmable Logic Device Family Data Sheet Table 17. EPM3032A Internal Timing Parameters (Part Symbol Parameter t PIA delay PIA t Low–power adder LPA Table 18. EPM3064A External Timing Parameters Symbol Parameter t Input to non–registered ...

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Table 19. EPM3064A Internal Timing Parameters (Part Symbol Parameter t Input pad and buffer delay IN t I/O input pad and buffer IO delay t Shared expander delay SEXP t Parallel expander delay PEXP t Logic array ...

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MAX 3000A Programmable Logic Device Family Data Sheet Table 19. EPM3064A Internal Timing Parameters (Part Symbol Parameter t Register clear time CLR t PIA delay PIA t Low–power adder LPA Table 20. EPM3128A External Timing Parameters Symbol ...

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Table 20. EPM3128A External Timing Parameters Symbol Parameter f Maximum internal ACNT array clock frequency Table 21. EPM3128A Internal Timing Parameters (Part Symbol Parameter t Input pad and buffer delay IN t I/O input pad and buffer ...

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MAX 3000A Programmable Logic Device Family Data Sheet Table 21. EPM3128A Internal Timing Parameters (Part Symbol Parameter t Register setup time SU t Register hold time H t Register delay RD t Combinatorial delay COMB t Array ...

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Table 22. EPM3256A External Timing Parameters Symbol Parameter t Minimum global clock CNT period f Maximum internal global CNT clock frequency t Minimum array clock ACNT period f Maximum internal array ACNT clock frequency Table 23. EPM3256A Internal Timing Parameters ...

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MAX 3000A Programmable Logic Device Family Data Sheet Table 23. EPM3256A Internal Timing Parameters (Part Symbol Parameter t Output buffer enable delay, slow ZX3 slew rate = 2 3.3 V CCIO t ...

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Table 24. EPM3512A External Timing Parameters Symbol Parameter t Array clock hold time AH t Array clock to output delay ACO1 t Array clock high time ACH t Array clock low time ACL t Minimum pulse width for clear CPPW ...

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MAX 3000A Programmable Logic Device Family Data Sheet Table 25. EPM3512A Internal Timing Parameters (Part Symbol Parameter t Output buffer and pad delay, OD3 slow slew rate = 2 3.3 V CCIO ...

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Power Supply power (P) versus frequency (f devices is calculated with the following equation: Consumption The P and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera The I ...

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MAX 3000A Programmable Logic Device Family Data Sheet Figure 12. I vs. Frequency for MAX 3000A Devices CC EPM3032A 3 Room Temperature 30 25 Typical Active (mA Low Power ...

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Figure 13. I vs. Frequency for MAX 3000A Devices CC EPM3256A 300 Room Temperature 250 200 Typical I CC 150 Active (mA) 100 Low Power Frequency (MHz) Altera Corporation MAX 3000A Programmable ...

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MAX 3000A Programmable Logic Device Family Data Sheet Device See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin–out information. Pin–Outs Figures 14 MAX 3000A devices. Figure 14. 44–Pin PLCC/TQFP Package Pin–Out Diagram Package outlines not drawn ...

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Figure 15. 100–Pin TQFP Package Pin–Out Diagram Package outline not drawn to scale. Figure 16. 144–Pin TQFP Package Pin–Out Diagram Package outline not drawn to scale Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Pin 1 EPM3064A EPM3128A ...

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MAX 3000A Programmable Logic Device Family Data Sheet Figure 17. 208–Pin PQFP Package Pin–Out Diagram Package outline not drawn to scale Pin 1 Pin EPM3256A EPM3512A Pin 157 Pin 105 Altera Corporation ...

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Figure 18. 256-Pin FineLine BGA Package Pin-Out Diagram Package outline not drawn to scale Indicates Location of Ball A1 EPM3512A Revision The information contained in the MAX 3000A Programmable Logic Device Data Sheet version 3.5 supersedes information published in previous ...

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MAX 3000A Programmable Logic Device Family Data Sheet Version 3.3 The following changes were made in the MAX 3000A Programmable Logic Device Data Sheet version 3.3: ■ ■ ■ ■ Version 3.2 The following change were made in the MAX ...