AD9518-0A-PCBZ AD [Analog Devices], AD9518-0A-PCBZ Datasheet - Page 11

• Manufacturer Part Number: AD9518-0A-PCBZ
• Description: 6-Output Clock Generator
• Manufacturer: AD [Analog Devices]

Data Sheet
LD, STATUS, AND REFMON PINS
Table 15.
Parameter
OUTPUT CHARACTERISTICS
MAXIMUM TOGGLE RATE
ANALOG LOCK DETECT
REF1, REF2, AND VCO FREQUENCY STATUS MONITOR
LD PIN COMPARATOR
POWER DISSIPATION
Table 16.
Parameter
POWER DISSIPATION, CHIP
POWER DELTAS, INDIVIDUAL FUNCTIONS
Output Voltage High (V
Output Voltage Low (V
Capacitance
Normal Range
Extended Range (REF1 and REF2 Only)
Trip Point
Hysteresis
Power-On Default
Full Operation
PD Power-Down
PD Power-Down, Maximum Sleep
V
VCO Divider
REFIN (Differential)
REF1, REF2 (Single-Ended)
VCO
PLL
Channel Divider
LVPECL Channel (Divider Plus Output Driver)
LVPECL Driver
CP
Supply
OL
OH
)
)
Min
Min
2.7
1.02
8
Rev. C | Page 11 of 64
Typ
0.76
1.1
75
31
4
30
20
4
70
75
30
160
90
Typ
100
3
1.6
260
0.4
Max
1.7
185
4.8
Max
1.0
Unit
V
V
MHz
pF
MHz
kHz
V
mV
Unit
W
W
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
Test Conditions/Comments
When selected as a digital output (CMOS); there are other
modes in which these pins are not CMOS digital outputs;
see Table 44, Register 0x017, Register 0x01A, and
Register 0x01B
Applies when mux is set to any divider or counter output,
or PFD up/down pulse; also applies in analog lock detect
mode; usually debug mode only; beware that spurs may
couple to output when any of these pins are toggling
On-chip capacitance; used to calculate RC time constant
for analog lock detect readback; use a pull-up resistor
Frequency above which the monitor always indicates the
presence of the reference
Frequency above which the monitor always indicates the
presence of the reference
Test Conditions/Comments
No clock; no programming; default register values;
does not include power dissipated in external resistors
PLL on; internal VCO = 2750 MHz; VCO divider = 2;
all channel dividers on; six LVPECL outputs at 687.5 MHz;
does not include power dissipated in external resistors
PD pin pulled low; does not include power dissipated
in terminations
PD pin pulled low; PLL power-down, Register 0x010[1:0] =
01b; SYNC power-down, Register 0x230[2] = 1b; REF for
distribution power-down, Register 0x230[1] = 1b
PLL operating; typical closed-loop configuration
Power delta when a function is enabled/disabled
VCO divider bypassed
All references off to differential reference enabled
All references off to REF1 or REF2 enabled; differential
reference not enabled
CLK input selected to VCO selected
PLL off to PLL on, normal operation; no reference
enabled
Divider bypassed to divide-by-2 to divide-by-32
No LVPECL output on to one LVPECL output on,
independent of frequency
Second LVPECL output turned on, same channel
AD9518-0