AD9518-4A-PCBZ AD [Analog Devices], AD9518-4A-PCBZ Datasheet - Page 25

• Manufacturer Part Number: AD9518-4A-PCBZ
• Description: 6-Output Clock Generator with Integrated 1.6 GHz VCO
• Manufacturer: AD [Analog Devices]

Data Sheet
Clock Distribution or External VCO < 1600 MHz
When the external clock source to be distributed or the external
VCO/VCXO is less than 1600 MHz, a configuration that bypasses
the VCO divider can be used. This configuration differs from the
High Frequency Clock Distribution—CLK or External VCO >
1600 MHz section only in that the VCO divider (divide-by-2/
divide-by-3/divide-by-4/divide-by-5/divide-by-6) is bypassed.
This limits the frequency of the clock source to <1600 MHz (due
to the maximum input frequency allowed at the channel dividers).
Configuration and Register Settings
For clock distribution applications where the external clock is
less than 1600 MHz, use the register settings shown in Table 24.
Table 24. Settings for Clock Distribution < 1600 MHz
Register
0x010[1:0] = 01b
0x1E1[0] = 1b
0x1E1[1] = 0b
When using the internal PLL with an external VCO of <1600 MHz,
the PLL must be turned on.
REFIN (REF1)
REFIN (REF2)
BYPASS
RESET
SYNC
SCLK
SDIO
SDO
CLK
CLK
PD
CS
LF
REF1
REF2
REGULATOR (LDO)
LOW DROPOUT
VCO
Function
PLL asynchronous power-down (PLL off )
Bypass the VCO divider as source for
distribution section
CLK selected as the source
AD9518-4
CONTROL
DIGITAL
SERIAL
SWITCHOVER
STATUS
LOGIC
REFERENCE
PORT
REF_ SEL
STATUS
VS
PRESCALER
2, 3, 4, 5, OR 6
P, P + 1
1
DIVIDE BY
Figure 30. Clock Distribution or External VCO <1600 MHz
GND
0
VCO STATUS
N DIVIDER
DIVIDER
R
COUNTERS
DISTRIBUTION
REFERENCE
A/B
RSET
Rev. B | Page 25 of 64
DIVIDE BY
DIVIDE BY
DIVIDE BY
1 TO 32
1 TO 32
1 TO 32
PROGRAMMABLE
PROGRAMMABLE
R DELAY
N DELAY
REFMON
Table 25. Settings for Using Internal PLL with External VCO <
1600 MHz
Register
0x1E1[0] = 1b
0x010[1:0] = 00b
An external VCO/VCXO requires an external loop filter that
must be connected between CP and the tuning pin of the
VCO/VCXO. This loop filter determines the loop bandwidth
and stability of the PLL. Make sure to select the proper PFD
polarity for the VCO/VCXO being used.
Table 26. Setting the PFD Polarity
Register
0x010[7] = 0b
0x010[7] = 1b
After the appropriate register values are programmed,
Register 0x232 must be set to 0x01 for the values to take effect.
FREQUENCY
DETECTOR
DETECT
PHASE
LOCK
Function
Bypass the VCO divider as source for distribution
section
PLL normal operation (PLL on), along with
other appropriate PLL settings in Register 0x010
to Register 0x01D
Function
PFD polarity positive (higher control voltage
produces higher frequency)
PFD polarity negative (higher control
voltage produces lower frequency)
CPRSET VCP
CHARGE
PUMP
HOLD
LVPECL
LVPECL
LVPECL
AD9518-4
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
OUT5
OUT5
LD
CP
STATUS