CAT5409WI25 ONSEMI [ON Semiconductor], CAT5409WI25 Datasheet - Page 8

• Manufacturer Part Number: CAT5409WI25
• Manufacturer: ONSEMI [ON Semiconductor]

CAT5409
INSTRUCTION AND REGISTER
DESCRIPTION
SLAVE ADDRESS BYTE
The first byte sent to the CAT5409 from the master/
processor is called the Slave/DPP Address Byte. The
most significant four bits of the Device Type address
are a device type identifier. These bits for the
CAT5409 are fixed at 0101[B] (refer to Table 1).
The next four bits, A3 - A0, are the internal slave
address and must match the physical device address
which is defined by the state of the A3 - A0 input pins
for the CAT5409 to successfully continue the
command sequence. Only the device which slave
address matches the incoming device address sent by
the master executes the instruction. The A3 - A0
inputs can be actively driven by CMOS input signals
or tied to V
Table 1. Identification Byte Format
Table 2. Instruction Byte Format
Doc. No. MD-2010 Rev. M
CC
or V
(MSB)
(MSB)
SS
ID3
I3
0
.
ID2
I2
1
Device Type
Instruction
Identifier
Opcode
ID1
I1
0
ID0
I0
1
8
INSTRUCTION BYTE
The next byte sent to the CAT5409 contains the
instruction and register pointer information. The four
most significant bits used provide the instruction
opcode I [3:0]. The R1 and R0 bits point to one of the
four data registers of each associated potentiometer.
The least two significant bits point to one of four Wiper
Control Registers. The format is shown in Table 2.
Data Register Selection
Data Register Selected
R1
A3
Data Register
Selection
DR0
DR1
DR2
DR3
R0
Slave Address
A2
WCR/Pot Selection
P1
A1
Characteristics subject to change without notice
R1
0
0
1
1
(LSB)
(LSB)
© 2009 SCILLC. All rights reserved.
A0
P0
R0
0
1
0
1