MAX7057 MAXIM [Maxim Integrated Products], MAX7057 Datasheet - Page 16

• Manufacturer Part Number: MAX7057
• Description: 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter
• Manufacturer: MAXIM [Maxim Integrated Products]

300MHz to 450MHz Frequency-Programmable
ASK/FSK Transmitter
These values are internally summed with 16, and thus,
the min and max divider becomes approximately 19
and 28. These limits MUST be followed, to prevent the
delta-sigma number generator from overflowing.
Table 12. Frequency Load Register (Address: 0x06)
Table 13. Data In Register (Address: 0x07)
Table 14. Enable Register (Address: 0x08)
Table 15. Configuration 1 Register (Address: 0x09)
Table 16. General-Purpose Output Selector (gposel[2:0]) for Configuration 1 Register
16
DECIMAL
BIT
BIT
BIT
BIT
2-0
7-3
______________________________________________________________________________________
0
0
0
0
1
2
3
4
5
6
7
RESERVED “0” RESERVED. Set to 0 for normal operation.
gposel[2:0]
enable_bit
datain_bit
BINARY
NAME
NAME
NAME
NAME
fload
000
001
010
011
100
101
110
111
Effectively changes the PLL frequency to the ones written in registers 2–5. This is a self-reset bit,
and is reset to zero after the operation is completed.
SPI equivalent of DIN, where the transmitted data can be controlled through the SPI interface. It
should be kept low (0) if only the external DIN pin is used. The external DIN pin should also be kept
low (0) if the SPI datain_bit is used.
SPI equivalent of ENABLE. It should be kept low (0) if the external ENABLE pin is used. The external
ENABLE pin should also be kept low (0) if the SPI enable_bit is used.
3-bit GPO selector
CKOUT_SDO
RESERVED
RESERVED
TxREADY
datain_bit
NoXTAL
CKOUT
GPO
SDO
Clock/SDO Output. Outputs clock when CS is high and clock output is enabled;
outputs SDO when CS is low.
SPI Serial Data Output (SDO)
Clock Output
RESERVED
RESERVED
Internal Crystal Oscillator Status. High means oscillator is NOT in operation.
Transmitter Ready Status. High means PLL is locked and MAX7057 is ready to
transmit data.
A copy of datain_bit
Whenever all of the fhi[11:0] and flo[11:0] are zero, only
an integer divider is used, and the delta-sigma modula-
tor is not in operation. This allows lower current opera-
tion. The 600kHz PLL bandwidth could be used in this
mode to reduce phase noise.
FUNCTION
FUNCTION
FUNCTION
FUNCTION
DESCRIPTION