SY55859L_10 MICREL [Micrel Semiconductor], SY55859L_10 Datasheet - Page 10

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SY55859L_10

Manufacturer Part Number
SY55859L_10
Description
3.3V, 3.2Gbps Dual 2X2 Crosspoint Switch
Manufacturer
MICREL [Micrel Semiconductor]
Datasheet
Application Information
The eight TTL compliant inputs to SY55859L are ENA0,
ENA1, ENB0 ENB1, SELA0, SELA1, SELB0 and
SELB1. These high impedance inputs do not default to a
stable logic state when left unconnected. Therefore,
these TTL compliant inputs cannot be left floating.
Connect these inputs to a valid control signal, or
hardwire to V
The four enable TTL inputs, when driven low, disable the
corresponding output stage. This reduces
consumption. Disabled output stages do not go into a
high impedance state. Rather, each pin of a disabled
output stage pair goes high through its respective 50Ω
source termination.
Micrel, Inc.
January 2010
CC
or GND.
power
10
The delay from a logic transition on an enable input to
the corresponding effect on the CML output is not
defined in the tables of this data sheet. This delay is 3ns
typical, and 10ns maximum. Please note that, for cases
where highly capacitive lines are being driven, the RC
effects of the line may make this delay longer.
The delay from a logic transition on a select input to the
corresponding CML output is also not defined in the
tables. It is 300psec typical, 500psec maximum.
For best performance, use good high frequency layout
techniques, filter V
connections short. Use multiple vias where possible.
Also, use controlled impedance transmission lines to
interface with the SY55859L data inputs and outputs.
hbwhelp@micrel.com
CC
supplies, and keep ground
or (408) 955-1690
M9999-012110-A
SY55859L

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