MCP3202-BI/MS MICROCHIP [Microchip Technology], MCP3202-BI/MS Datasheet - Page 13

• Manufacturer Part Number: MCP3202-BI/MS
• Description: 2.7V Dual Channel 12-Bit A/D Converter with SPI Serial Interface
• Manufacturer: MICROCHIP [Microchip Technology]

5.0
5.1
Communication with the MCP3202 is done using a
standard SPI-compatible serial interface. Initiating
communication with the device is done by bringing the
CS line low. See Figure 5-1. If the device was powered
up with the CS pin low, it must be brought high and
back low to initiate communication. The first clock
received with CS low and D
bit. The SGL/DIFF bit and the ODD/SIGN bit follow the
start bit and are used to select the input channel config-
uration. The SGL/DIFF is used to select single ended
or psuedo-differential mode. The ODD/SIGN bit selects
which channel is used in single ended mode, and is
used to determine polarity in pseudo-differential mode.
Following the ODD/SIGN bit, the MSBF bit is transmit-
ted to and is used to enable the LSB first format for the
device. If the MSBF bit is high, then the data will come
from the device in MSB first format and any further
clocks with CS low will cause the device to output
zeros. If the MSBF bit is low, then the device will output
the converted word LSB first after the word has been
transmitted in the MSB first format. See Figure 5-2.
Table 5-1 shows the configuration bits for the
MCP3202. The device will begin to sample the analog
input on the second rising edge of the clock, after the
start bit has been received. The sample period will end
on the falling edge of the third clock following the start
bit.
FIGURE 5-1:
© 2006 Microchip Technology Inc.
CS
CLK
D
D
IN
OUT
SERIAL COMMUNICATIONS
Overview
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros
indefinitely. See Figure 5-2 below for details on obtaining LSB first data.
** t
high impedance node, leaving the CLK running to clock out the LSB-first data or zeros.
DATA
: during this time, the bias current and the comparator power down while the reference input becomes a
Communication with the MCP3202 using MSB first format only.
Start
SGL/
DIFF
t
SUCS
HI-Z
ODD/
SIGN BF
t
SAMPLE
IN
MS
high will constitute a start
Null
Bit B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
t
CYC
t
CONV
Don’t Care
On the falling edge of the clock for the MSBF bit, the
device will output a low null bit. The next sequential
12 clocks will output the result of the conversion with
MSB first as shown in Figure 5-1. Data is always output
from the device on the falling edge of the clock. If all
12 data bits have been transmitted and the device con-
tinues to receive clocks while the CS is held low, (and
MSBF = 1), the device will output the conversion result
LSB first as shown in Figure 5-2. If more clocks are pro-
vided to the device while CS is still low (after the LSB
first data has been transmitted), the device will clock
out zeros indefinitely.
If necessary, it is possible to bring CS low and clock in
leading zeros on the D
often done when dealing with microcontroller-based
SPI ports that must send 8 bits at a time. Refer to
Section 6.1 for more details on using the MCP3202
devices with hardware SPI ports.
TABLE 5-1:
Single Ended
DifferentiaL
Pseudo-
Mode
Mode
Configuration Bits for the MCP3202.
t
t
Sgl/
CSH
Diff
DATA
1
1
0
0
Config
IN
**
Bits
line before the start bit. This is
Odd/
sign
0
1
0
1
Start
MCP3202
HI-Z
t
CYC
SGL/
DIFF
IN+
IN-
Selection
—
Channel
0
+
DS21034D-page 13
ODD/
SIGN
IN+
IN-
—
1
+
GND
-
-