MCP3204-BIP MICROCHIP [Microchip Technology], MCP3204-BIP Datasheet - Page 16

• Manufacturer Part Number: MCP3204-BIP
• Description: 2.7V 4-Channel/8-Channel 12-Bit A/D Converters with SPI Serial Interface
• Manufacturer: MICROCHIP [Microchip Technology]

MCP3204/3208
6.0
6.1
With most microcontroller SPI ports, it is required to
send groups of eight bits. It is also required that the
microcontroller SPI port be configured to clock out data
on the falling edge of clock and latch data in on the rising
edge. Because communication with the MCP3204/3208
devices may not need multiples of eight clocks, it will be
necessary to provide more clocks than are required.
This is usually done by sending ‘leading zeros’ before
the start bit. As an example, Figure 6-1 and Figure 6-2
shows how the MCP3204/3208 can be interfaced to a
MCU with a hardware SPI port. Figure 6-1 depicts the
operation shown in SPI Mode 0,0 which requires that the
SCLK from the MCU idles in the ‘low’ state, while
Figure 6-2 shows the similar case of SPI Mode 1,1
where the clock idles in the ‘high’ state.
FIGURE 6-1:
FIGURE 6-2:
DS21298B-page 16
MCU Transmitted Data
X = Don’t Care Bits
X = Don’t Care Bits
(Aligned with falling
edge of clock)
MCU Received Data
(Aligned with rising
SCLK
SCLK
D
D
MCU Received Data
MCU Transmitted Data
(Aligned with rising
edge of clock)
OUT
OUT
D
(Aligned with falling
D
CS
CS
edge of clock)
IN
IN
edge of clock)
APPLICATIONS INFORMATION
Using the MCP3204/3208 with
Microcontroller (MCU) SPI Ports
on rising edges of SCLK
MCU latches data from A/D Converter
MCU latches data from A/D Converter
on rising edges of SCLK
SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).
SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).
0
1
1
?
?
Data stored into MCU receive register
Data stored into MCU receive register
0
0
2
2
after transmission of first 8 bits
after transmission of first 8 bits
?
?
0
0
3
3
?
?
0
0
HI-Z
HI-Z
4
4
?
?
0
0
5
5
?
?
Start
Start
Start
Bit
1
0
Data is clocked out of
A/D Converter on falling edges
6
6
?
?
Start
SGL/
DIFF
SGL/
DIFF
SGL/
DIFF
Bit
1
Data is clocked out of
A/D Converter on falling edges
7
7
?
SGL/
DIFF
?
D2
D2
8
D2
?
?
8
D2
D1
D1
D1
9
9
?
?
Preliminary
Data stored into MCU receive register
Data stored into MCU receive register
D1
DO
after transmission of second 8 bits
DO
after transmission of second 8 bits
DO
10
10
?
?
DO
X
11
11
?
?
NULL
NULL
X
BIT
BIT
X
12
12
(Null)
(Null)
0
0
X
B11
B11
X
As shown in Figure 6-1, the first byte transmitted to the
A/D Converter contains five leading zeros before the
start bit. Arranging the leading zeros this way produces
the output 12 bits to fall in positions easily manipulated
by the MCU. The MSB is clocked out of the A/D Con-
verter on the falling edge of clock number 12. After the
second eight clocks have been sent to the device, the
MCUs receive buffer will contain three unknown bits
(the output is at high impedance for the first two clocks),
the null bit and the highest order four bits of the conver-
sion. After the third byte has been sent to the device, the
receive register will contain the lowest order eight bits of
the conversion results. Easier manipulation of the con-
verted data can be obtained by using this method.
Figure 6-2 shows the same thing in SPI Mode 1,1
which requires that the clock idles in the high state. As
with mode 0,0, the A/D Converter outputs data on the
falling edge of the clock and the MCU latches data from
the A/D Converter in on the rising edge of the clock.
13
13
B11
B11
X
B10
B10
X
14
14
B10
B10
X
B9
B9
X
15
15
B9
B9
X
X
B8
16
B8
B8
B8
16
X
B7
B7
X
Don’t Care
17
17
B7
Don’t Care
B7
Data stored into MCU receive register
Data stored into MCU receive register
X
X
B6
B6
after transmission of last 8 bits
18
after transmission of last 8 bits
18
B6
B6
X
X
B5
B5
19
19
B5
1999 Microchip Technology Inc.
B5
X
X
B4
B4
20
20
B4
B4
X
X
B3
B3
21
21
B3
B3
X
X
B2
B2
22
22
B2
B2
X
X
B1
B1
23
23
B1
B1
X
X
B0
B0
24
24
B0
B0
X