AD7366-5ARUZ AD [Analog Devices], AD7366-5ARUZ Datasheet - Page 14

• Manufacturer Part Number: AD7366-5ARUZ
• Description: True Bipolar Input, Dual 1us, 12-Bit, 2-Channel SAR ADC
• Manufacturer: AD [Analog Devices]

AD7366
MODES OF OPERATION
The mode of operation of the AD7366 is selected by the (logic) state of the CONVST signal at the end of a conversion. There are two
possible modes of operation: normal mode and shut-down mode. These modes of operation are designed to provide flexible power
management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for differing application
requirements.
NORMAL MODE
This mode is intended for applications needing fast throughput
rates since the user does not have to worry about any power-up
times with the AD7366 remaining fully powered at all times.
Figure 7 shows the general mode of operation of the AD7366 in
this mode.
The conversion is initiated on the falling edge of CONVST as
described in the Circuit Information section. To ensure that the
part remains fully powered up at all times, CONVST must be at
logic state high prior to the BUSY signal going low. If CONVST
is at logic state low when the BUSY signal goes low, the
analogue circuitry will power down and the part will cease
converting. The BUSY signal remains high for the duration of
the conversion. The CS pin must be brought low to bring the
data bus out of three-sate, subsequently twelve serial clock
cycles are required to read the conversion result. The D
SHUT-DOWN MODE
This mode is intended for use in applications where slow
throughput rates are required. This mode is suited to
applications where a series of conversions performed at a
relatively high throughput rate are followed by a long period of
inactivity and thus, shut-down. When the AD7366 is in full
power-down, all analog circuitry is powered down. As already
stated, the falling edge of CONVST initiates the conversion.
The BUSY output subsequently goes high to indicate that the
conversion is in progress. Once the conversion is completed, the
BUSY output returns low. If the CONVST signal is at logic low
when BUSY goes low then the part will enter shut-down at the
CONVST
BUSY
SCLK
CS
t 2
SERIAL READ OPERATION
t 1
t convert
Figure 7. Normal Mode Operation
OUT
lines
Rev. PrG | Page 14 of 17
t
1
3
return to three-state when CS is brought high and not after 12
SCLK cycles has elapsed. If CS is left low for a further 12 SCLK
cycles, the result from the other on chip ADC is also accessed
on the same D
Interface section)
Once 24 SCLK cycles have elapsed, the D
three-state when CS is brought high and not on the 24
falling edge. If CS is brought high prior to this, the D
returns to three-state at that point. Thus, CS must be brought
high once the read is completed, as the bus does not
automatically return to three-state upon completion of the dual
result read.
Once a data transfer is complete and D
returned to three-state, another conversion can be initiated after
the quiet time, t
again.
end of the conversion phase. While the part is in shut-down
mode the digital output code from the last conversion on each
ADC can still be read from the D
CS
Section. The D
back to logic high.
To exit full power-down and power up the AD7366, A rising
edge of CONVST is required. After the required power up time
has elapsed, CONVST may be brought low again to initiate
another conversion, as shown in Figure 8 See the Power up time
section for power-up times associated with the AD7366.
must be brought low as described in the Serial Interface
OUT
OUT
QUIET
line, as shown in Figure 10 (see the Serial
pins return to three-state once
Preliminary Technical Data
, has elapsed by bringing CONVST low
t quiet
12
OUT
pins. To read the D
OUT
OUT
A and D
line returns to
CS
OUT
OUT
is brought
B have
th
OUT
SCLK
line
data