MCP3301T MICROCHIP [Microchip Technology], MCP3301T Datasheet - Page 17

• Manufacturer Part Number: MCP3301T
• Description: 13-Bit Differential Input, Low Power A/D Converter with SPI Serial Interface
• Manufacturer: MICROCHIP [Microchip Technology]

5.0
5.1
The MCP3301MCP3301 A/D converter employs a con-
ventional SAR architecture. With this architecture, the
potential between the IN+ and IN- inputs are
simultaneously sampled and stored with the internal
sample circuits for 1.5 clock cycles (t
this sample time, the input hold switches of the
converter open and the device uses the collected
charge to produce a serial 13-bit binary two’s
complement output code. This conversion process is
driven by the external clock and must include 13 clock
cycles, one for each bit. During this process, the most
significant bit (MSB) is output first. This bit is the sign
bit and indicates whether the IN+ input or the IN- input
is at a higher potential.
FIGURE 5-1:
 2011 Microchip Technology Inc.
IN+
IN-
Hold
Hold
APPLICATIONS INFORMATION
Conversion Description
C
C
SAMP
SAMP
Simplified Block Diagram.
+
-
Comp
CDAC
ACQ
D
13-Bit SAR
). Following
OUT
Register
Shift
5.2
The analog input of the MCP3301 is easily driven either
differentially or single-ended. Any signal that is
common to the two input channels will be rejected by
the common mode rejection of the device. During the
charging time of the sample capacitor, a small charging
current will be required. For low source impedances,
this input can be driven directly. For larger source
impedances, a larger acquisition time will be required,
due to the RC time constant that includes the source
impedance. For the A/D Converter to meet specifica-
tion, the charge holding capacitor (C
given enough time to acquire a 13-bit accurate voltage
level during the 1.5 clock cycle acquisition period.
An analog input model is shown in
model is accurate for an analog input, regardless of
whether it is configured as a single-ended input or the
IN+ and IN- input in differential mode. In this diagram,
it is shown that the source impedance (R
internal sampling switch (R
affecting the time that is required to charge the capaci-
tor (C
ance with no additional acquisition time increases the
offset, gain, and integral linearity errors of the conver-
sion. To overcome this, a slower clock speed can be
used to allow for the longer charging time.
shows the maximum clock speed associated with
source impedances.
FIGURE 5-2:
vs. Source Resistance (R
INL.
1.8
1.6
1.4
1.2
0.8
0.6
0.4
0.2
1
0
SAMPLE
100
Driving the Analog Input
). Consequently, a larger source imped-
Input Resistance (ohms)
1000
Maximum Clock Frequency
S
SS
) to maintain ±1 LSB
MCP3301
) impedance, directly
10000
DS21700D-page 17
SAMPLE
Figure
S
) adds to the
Figure 5-2
) must be
5-3. This
100000