MAX5003C/D MAXIM [Maxim Integrated Products], MAX5003C/D Datasheet - Page 14

• Manufacturer Part Number: MAX5003C/D
• Description: High-Voltage PWM Power-Supply Controller
• Manufacturer: MAXIM [Maxim Integrated Products]

7) Low-ESR/ESL ceramic capacitors were used in this
High-Voltage PWM
Power-Supply Controller
14
DC(V
where:
R
V
V
DC
For this application circuit, a 10% margin is reason-
able, so the value used is 50kΩ. This gives a maxi-
mum duty cycle of 50%. The maximum duty cycle
can now be expressed as:
where:
V
DC(V
0.5V and 2.5V are the values at the beginning and
end of the PWM ramp.
The term ƒ
for clock frequency variation. If the clock is running
at 300kHz and the input voltage is fixed, then the
duty cycle is a scaled portion of the maximum duty
cycle, determined by V
application. The output filter is made by two 22µF
ceramic capacitors in parallel. Normally, the ESR of
a capacitor is a dominant factor determining the rip-
ple, but in this case it is the capacitor value.
Calculating
MIN
UVL
CON
MAXTON
CON,VIN
______________________________________________________________________________________
MAX
CON
= Minimum power-line voltage
= Power-line trip voltage
= Voltage at the CON pin, input of the PWM
DC(V
DC(V
DC(2.5V,V
DC(2.5V,V
DC(0.5V,V
DC(0.5V,V
(V
ƒ
)
comparator
I
SW
, V
OUT
MIN
=
= Resistor between the MAXTON pin and
≈
SW






CON MIN
CON MAX
IN
ground
⋅
V
V
) = Maximum duty cycle at minimum
C
CON
CON
) = Duty cycle, function of V
/ ƒ
2.0V
2.0V
,V
,V
=
NOM
MIN
MAX
MIN
MAX
power-line voltage
−
- 0.5V
V
300
IN
0.5V
)
)
)
)
) =
varies from 0.8 to 1.2 to allow
)
=
=
CON
kHz
=
=






=
50%
0
1



25%



A
0



36V
V
V



.
⋅
V
IN
V
MIN
44
IN
V
CON
CON



µ






F
2.0V



ƒ
2.0V
ƒ
NOM
ƒ
SW
−
ƒ
NOM
=
−
SW
0.5V
0.5V



76



50%
⋅
mV
DC






MAX(VMIN)
50%
CON
25%
and
The DC accuracy of the regulator is a function of the
DC gain. For 1% accuracy, a DC gain of 20 is required.
Since the maximum midband gain for a stable
response is 16, an integrator with a flat midband gain
given by a zero is used. The midband gain is less than
16, to preserve stability, and the DC gain is much larger
than 20, to achieve high DC accuracy.
Optimization on the bench showed that a midband gain
of 5 gave fast transient response and settling with no
ringing. The zero was pushed as high in frequency as
possible without losing stability. The zero must be a
factor of two or so below the system unity-gain frequen-
cy (crossover frequency) at minimum load. With the
8)The PWM gain can be calculated from:
the ripple will be a fraction of this depending on the
duty cycle. For a 50% duty cycle, the ripple due to
the capacitance is approximately 45mV.
Note that while the above formula incorporates the
product of the maximum duty cycle and V
independent of V
PWM gain is +3.0V/V. For a 10% load (R
the gain is multiplied by the square root of 10 and
becomes +10V/V. The pole of the system due to the
output filter is 1 / 2πRC, where R is the load resis-
tance and C the filter capacitor. Choosing a capaci-
tor and calculating the pole frequency by:
it is 723Hz at full load. At 10% load it will be 72Hz,
since the load resistor is then 50Ω instead of 5Ω. The
total loop gain is equal to the PWM gain times the
gain in the combination of the voltage divider and
the error amplifier. The worst case for phase margin
is at full load. For a phase margin of 60 degrees, this
midband gain (G) must be set to be less than:
where:
ƒ
PM = Phase margin angle
A
U
PWM
= Unity-gain frequency of error amplifier
G
=
<
ƒ =
dV
dV
P
tan(
CON
OUT



PM A
ƒ
2
UErrorAmp
=
π
=
)
⋅ ⋅
⋅
R C
IN
2 L
1
2 L
L
. For 1A output (R
PWM
⋅
⋅
PRI SW
R
PRI SW
L
R
L

 =

L
⋅
⋅
ƒ
⋅
ƒ
ƒ
P
=









2
V
2.0V
2 0
π
36
MIN
1 7 3 723
.
⋅ ⋅
.
V
5
V
Ω
1
⋅ ⋅






1
MHz
DC
50
44
L
%
MAX VMIN
µ
= 5Ω), the
F
L
≅
Hz



3
(
= 50Ω),
IN
, it is
)