LM9810 NSC [National Semiconductor], LM9810 Datasheet - Page 19
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LM9810
Manufacturer Part Number
LM9810
Description
LM9810/20 10/12-Bit Image Sensor Processor Analog Front End
Manufacturer
NSC [National Semiconductor]
Datasheet
1.LM9810.pdf
(21 pages)
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nation of the applied
synchronize the applied
will go low after the falling edge of
of
then go high. It will stay high until the next falling edge of
is clocked by
ADC clock timing relationship.
The LM9810/20 is a densely designed, mixed-signal, monolithic
semiconductor. In creating the timing for the LM9810/20, it must
be considered that internal events, such as ADC sampling, and
output data bus switching can potentially affect coincident events
such as input signal sampling or offset DAC settling. One event
can interfere with another by coupling noise on shared resources
such as the supply lines, internal voltage references, or the silicon
substrate.
To optimize the performance of the LM9810/20,
be timed so that the input signal hold times do not coincide with
output data switching and ADC clock transitions. In other words,
the rising and falling edges of
close to ADC clock edges or to output data transitions.
edges should be at least 20ns away from ADC clock edges to
avoid interference between the ADC and the sampler.
edges should also be placed at least 40ns after output data tran-
sition times to avoid transition noise coupling.
Figure 6 is an example of
requirements at the maximum
gram 6,
will keep them more than 20ns away from ADC transitions, and
40ns after output data transitions.
SampCLK
ADC Clock
(internal)
MCLK
D5 - D0
MCLK
. The ADC clock will stay low for two
SampCLK
Figure 6: LM9810/20 Relative Event Timing
MCLK
transitions occur on
. Figure 6 illustrates this
SampCLK
SampCLK
b11 - b6
SampCLK
and
MCLK
SampCLK
signal. The internal ADC clock
SampCLK
MCLK
frequency of 24MHz. In dia-
timing that will meet these
MCLK
signals.
should not be placed
is clocked by a rising
SampCLK
falling edges which
b5 - b0
MCLK
SampCLK
MCLK
,
cycles and
MCLK
is used to
SampCLK
SampCLK
SampCLK
should
, and
19
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