MAX519 MAXIM [Maxim Integrated Products], MAX519 Datasheet - Page 9

• Manufacturer Part Number: MAX519
• Description: 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs
• Manufacturer: MAXIM [Maxim Integrated Products]

these devices may share the bus. The MAX519 has 16
possible slave addresses. The eighth bit (LSB) in the
slave address byte should be low when writing to the
MAX517/MAX518/MAX519.
The MAX517/MAX518/MAX519 monitor the bus continu-
ously, waiting for a START condition followed by their
slave address. When a device recognizes its slave
address, it is ready to accept data.
A command byte follows the slave address. Figure 7
shows the format for the command byte. A command
byte is usually followed by an output byte unless it is
the last byte in the transmission. If it is the last byte, all
bits except PD (power-down) and RST (reset) are
Figure 4. A Complete Serial Transmission
Figure 5. All communications begin with a START condition and
end with a STOP condition, both generated by a bus master.
Figure 6. Address Byte
SCL
SDA
SDA
SCL
SLAVE ADDRESS BITS AD0, AD1, AD2, AND AD3 CORRESPOND TO THE LOGIC
STATE OF THE ADDRESS INPUT PINS.
SDA
SCL
START CONDITION
START CONDITION
0
1
MSB
The Command Byte and Output Byte
0
_______________________________________________________________________________________
SLAVE ADDRESS BYTE
SLAVE ADDRESS
AD3
1 or
1 or
AD2
AD1
LSB
AD0
ACK
LSB
STOP CONDITION
0
2-Wire Serial 8-Bit DACs with
MSB
ACK
COMMAND BYTE
ignored. If an output byte follows the command byte,
A0 of the command byte indicates the digital address
of the DAC whose input data latch receives the digital
output data. Set this bit to 0 when writing to the
MAX517. The data is transferred to the DAC’s output
latch during the STOP condition following the transmis-
sion. This allows both DACs of the MAX518/MAX519 to
be updated simultaneously (Figure 8).
Setting the PD bit high powers down the MAX517/
MAX518/MAX519 following a STOP condition (Figure
9a). If a command byte with PD set high is followed by
an output byte, the addressed DAC’s input latch will be
updated and the data will be transferred to the DAC’s
output latch following the STOP condition (Figure 9b).
Figure 7. Command Byte
SDA
SCL
R2, R1, R0: RESERVED BITS. SET TO 0.
RST: RESET BIT, SET TO 1 TO RESET ALL DAC REGISTERS.
PD: POWER-DOWN BIT. SET TO 1 TO PLACE THE DEVICE IN THE 4µA SHUTDOWN
A0: ADDRESS BIT. DETERMINES WHICH DAC'S INPUT LATCH RECEIVES THE 8 BITS
ACK: ACKNOWLEDGE BIT. THE MAX517/MAX518/MAX519 PULLS SDA LOW DURING
X: DON’T CARE.
LSB
OF DATA IN THE NEXT BYTE. SET TO 0 FOR MAX517.
MODE. SET TO 0 TO RETURN TO THE NORMAL OPERATIONAL STATE.
THE 9TH CLOCK PULSE.
MSB
ACK
R2
Rail-to-Rail Outputs
R1
MSB
R0
OUTPUT BYTE
RST
PD
X
LSB
X
ACK
STOP CONDITION
A0/0
LSB
ACK
9