MAXQ610_09 MAXIM [Maxim Integrated Products], MAXQ610_09 Datasheet - Page 21

• Manufacturer Part Number: MAXQ610_09
• Description: 16-Bit Microcontroller with Infrared Module
• Manufacturer: MAXIM [Maxim Integrated Products]

The lowest power mode of operation for the MAXQ610
is stop mode. In this mode, CPU state and memories
are preserved, but the CPU is not actively running.
Wake-up sources include external I/O interrupts, the
power-fail warning interrupt, or a power-fail reset. Any
time the microcontroller is in a state where code does
not need to be executed, the user software can put the
MAXQ610 into stop mode. The nanopower ring oscilla-
tor is an internal ultra-low-power (400nA), 8kHz ring
oscillator that can be used to drive a wake-up timer that
exits stop mode. The wake-up timer is programmable
by software in steps of 125µs up to approximately 8s.
The power-fail monitor is always on during normal oper-
ation. However, it can be selectively disabled during
stop mode to minimize power consumption. This fea-
ture is enabled using the power-fail monitor disable
Figure 11. Power-Fail Detection During Normal Operation
INTERNAL RESET
(ACTIVE HIGH)
V
V
V
PFW
POR
RST
16-Bit Microcontroller with Infrared Module
V
DD
______________________________________________________________________________________
A
B
C
Operating Modes
t < t
D
PFW
t ≥ t
PFW
E
(PFD) bit in the PWCN register. The reset default state
for the PFD bit is 1, which disables the power-fail moni-
tor function during stop mode. If power-fail monitoring
is disabled (PFD = 1) during stop mode, the circuitry
responsible for generating a power-fail warning or reset
is shut down and neither condition is detected. Thus,
the V
However, in the event that V
level, a POR is generated. The power-fail monitor is
enabled prior to stop mode exit and before code exe-
cution begins. If a power-fail warning condition (V
V
set on stop mode exit. If a power-fail condition is
detected (V
Figures 11, 12, and 13 show the power-fail detection
and response during normal and stop mode operation.
PFW
DD
) is then detected, the power-fail interrupt flag is
t ≥ t
PFW
F
< V
DD
RST
< V
condition does not invoke a reset state.
RST
), the CPU goes into reset.
G
Power-Fail Detection
t ≥ t
DD
PFW
falls below the POR
H
I
DD
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