MAX537 MAXIM [Maxim Integrated Products], MAX537 Datasheet
MAX537
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MAX537 Summary of contents
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... Offset, gain, and linearity are factory calibrated to provide the MAX536’s ±1LSB total unadjusted error. The MAX537 operates with ±5V supplies, while the MAX536 uses -5V and +12V to +15V supplies. ...
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... Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface ABSOLUTE MAXIMUM RATINGS V to AGND or DGND DD MAX536 ..................................................................-0.3V, +17V MAX537 ....................................................................-0.3V, + AGND or DGND ...............................................-7V, +0.3V SS SDI, SCK , CS, LDAC, TP, SDO to AGND or DGND.....................................-0.3V 0.3V) REFAB, REFCD to AGND or DGND .............-0.3V 0.3V) OUT_ to AGND or DGND ............................................. Maximum Current into Any Pin............................................50mA Stresses beyond those listed under “ ...
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Voltage-Output DACs with Serial Interface ELECTRICAL CHARACTERISTICS—MAX536 (continued +15V -5V, REFAB/REFCD = 10V, AGND = DGND = 0V otherwise noted. Typical values are at T PARAMETER SYMBOL MATCHING PERFORMANCE (T = +25°C) A ...
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... Note 4: Digital inputs at 2.4V; with digital inputs at CMOS levels, I Note 5: All input signals are specified with t Note 6: Serial data clocked out of SDO on SCK’s falling edge. (SDO is an open-drain output for the MAX536. The MAX537’s SDO pin has an internal active pull-up.) Note 7: Serial data clocked out of SDO on SCK’ ...
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... Voltage-Output DACs with Serial Interface ELECTRICAL CHARACTERISTICS—MAX537 (V = +5V -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V otherwise noted. Typical values are at T PARAMETER SYMBOL STATIC PERFORMANCE—ANALOG SECTION Resolution N Integral Nonlinearity INL Differential Nonlinearity DNL Offset Error Gain Error V Power-Supply DD PSRR Rejection Ratio ...
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... Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface ELECTRICAL CHARACTERISTICS—MAX537 (continued +5V -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V otherwise noted. Typical values are PARAMETER SYMBOL DIGITAL OUTPUT (SDO) Output High Voltage V OH Output Low Voltage V OL DYNAMIC PERFORMANCE ( ...
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... Note 4: Digital inputs at 2.4V; with digital inputs at CMOS levels, I Note 5: All input signals are specified with t Note 6: Serial data clocked out of SDO on SCK’s falling edge. (SDO is an open-drain output for the MAX536. The MAX537’s SDO pin has an internal active pull-up.) Note 7: Serial data clocked out of SDO on SCK’ ...
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Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface __________________________________________Typical Operating Characteristics (T = +25°C, unless otherwise noted.) A MAX536 INTEGRAL NONLINEARITY ERROR vs. REFERENCE VOLTAGE 1 - +15V 0 +12V ...
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Voltage-Output DACs with Serial Interface ____________________________Typical Operating Characteristics (continued +25°C, unless otherwise noted.) A MAX536 DYNAMIC RESPONSE (ALL BITS ON, OFF, ON) 5 s/div V = +15V -5V, REFAB = 5V 100pF ...
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... LOAD (k ) REFERENCE FEEDTHROUGH AT 4kHz REFAB, 1V/div 0V OUTA, AC-COUPLED, 100 V/div INPUT CODE = ALL 0s MAX537 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY 0.200 REFAB = 2.5Vp-p 0.175 0.150 0.125 R = 10k , C = 100pF L L 0.100 0.075 LOAD 0pF L L 0.050 ...
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... OUTA, 5mV/div V = +5V 10k DD L DIN TOGGLING AT OUTA = 1.25V MAX537 (ALL BITS ON TO ALL BITS OFF) CS, 5V/div OUTA, 5mV/div 1 s/div = -5V, REFAB = 2.5V 100pF 10k MAX537 DIGITAL FEEDTHROUGH SCK, 5V/div OUTA, AC-COUPLED, 20mV/div 100ns/div = -5V, REFAB = 2.5V HIGH ⁄ THE CLOCK RATE ...
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... Shift Register Clock Input Serial Data Output. SDO is the output of the internal shift register. SDO is enabled when CS is low. 11 SDO For the MAX536, SDO is an open-drain output. For the MAX537, SDO has an active pull- REFCD Reference Voltage Input for DAC C and DAC D ...
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... I/O I/O *THE SDO-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX536, BUT MAY BE USED FOR READBACK PURPOSES. **THE LDAC CONNECTION IS NOT REQUIRED WHEN USING THE 3-WIRE INTERFACE. † THE MAX537 HAS AN INTERNAL ACTIVE PULL- DD NOT NECESSARY. P Figure 3. Connections for SPI/QSPI ...
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Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface CS SCK 1 SDI D15 D14 D13 SDO Q15 .......... MSB FROM PREVIOUS WRITE Figure 4. 3-Wire Serial-Interface Timing Diagram (LDAC = GND ...
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... SDO defaults to Mode 1 timing. For the MAX536, SDO is an open-drain output that should be pulled up to +5V. The data sheet timing specifications for SDO use a 1k pull-up resistor. For the MAX537, SDO is a complementary output and does not require an external pull-up. Data Bits The test pin (TP) is used for pre-production analysis of the IC ...
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... C = 30pF), the maximum clock frequency is p < 20ns, RC 8.7MHz. from the following Figure 9 shows an alternate method of connecting several MAX536/MAX537s. In this configuration, the data bus PULL-UP common to all devices; data is not shifted through a - 2.4V daisy-chain. More I/O lines are required in this configu- ration because a dedicated chip-select input (CS) is required for each IC ...
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... Voltage-Output DACs with Serial Interface MAX536 SCK MAX537 SCK DIN SDI THE MAX537 HAS AN ACTIVE INTERNAL PULL-UP Figure 8. Daisy-Chaining MAX536/MAX537s with a 3-Wire Serial Interface DIN SCK LDAC CS1 CS2 CS3 CS LDAC MAX536 SCK MAX537 SDI Figure 9. Multiple devices sharing a common DIN line may be simultaneously updated by bringing LDAC low. CS1, CS2, CS3… are driven separately, thus controlling which data are written to devices 1, 2, 3… ...
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Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface __________Applications Information Interfacing to the M68HC11* PORT D of the 68HC11 supports SPI. The four registers used for SPI operation are the Serial Peripheral Control Register, the Serial Peripheral Status Register, the ...
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Voltage-Output DACs with Serial Interface Table 4. M68HC11 Programming Code ______________________________________________________________________________________ Calibrated, Quad, 12-Bit 19 ...
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... For a unipolar output, the output voltages and the reference inputs are the same polarity. Figure 10 shows the MAX536/MAX537 unipolar output circuit, which is also the typ- ical operating circuit. Table 5 lists the unipolar output codes. The MAX536/MAX537 outputs can be configured for bipolar operation using Figure 11’ ...
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... OUTB + AGND DGND V BIAS NOTES ARE FOR MAX537. Figure 13. AGND Bias Circuit R1 R2 +15V (+5V) – 10k V IS THE SELECTED REFERENCE INPUT FOR THE MAX536/MAX537. REF +15V (+5V REFAB DAC A AGND MAX536/MAX537 4 V DGND -5V DIGITAL INPUTS NOT SHOWN. ...
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... The typi- p-p cal -3dB frequency is 700kHz as shown in the Typical Operating Characteristics graphs. For the MAX537, with an input signal amplitude of 0.85mV , THD + N is typically less than 0.024% with a p-p 5k load in parallel with 100pF and input frequencies up to 100kHz, or with a 2k load in parallel with 100pF and input frequencies up to 95kHz ...
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... Wide SO MAX537BC/D 0°C to +70°C Dice* MAX537AEPE -40°C to +85°C 16 Plastic DIP MAX537BEPE -40°C to +85°C 16 Plastic DIP MAX537AEWE -40°C to +85°C 16 Wide SO MAX537BEWE -40°C to +85°C 16 Wide SO MAX537AMDE -55°C to +125°C 16 Ceramic SB** MAX537BMDE -55°C to +125°C 16 Ceramic SB** * Contact factory for dice specifications. ...
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Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface ________________________________________________________Package Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change ...