MAX5380-MAX5382 MAXIM [Maxim Integrated Products], MAX5380-MAX5382 Datasheet - Page 10

• Manufacturer Part Number: MAX5380-MAX5382
• Description: Low-Cost, Low-Power, 8-Bit DACs with 2-Wire Serial Interface in SOT23
• Manufacturer: MAXIM [Maxim Integrated Products]

device, followed by the MAX5380/MAX5381/MAX5382s’
preset slave address, a power-mode bit, the DAC data,
and finally, a STOP condition (Figure 6). The bus is then
free for another transmission.
SDA’s state is sampled and therefore must remain sta-
ble while SCL is high. Data is transmitted in 8-bit bytes.
Nine clock cycles are required to transfer each byte to
the MAX5380/MAX5381/MAX5382. Release SDA during
the 9th clock cycle since the selected device acknowl-
edges receipt of the byte by pulling SDA low during
this time. A series resistor on the SDA line may be
needed if the master’s output is forced high while the
selected device acknowledges (Figure 4).
The MAX5380/MAX5381/MAX5382 are available with
one of four preset slave addresses. Each address
option is identified by the suffix L, M, N, or P added to
the part number. The address is defined as the 7MSBs
sent by the master after a START condition. The
address options are 0x60, 0x62, 0x64, 0x66 (left justi-
fied with LSB set to 0). The 8th bit, typically used to
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
Figure 5. START and STOP Conditions
Figure 6. A Complete Serial Transmission
10
SDA
SDA
SCL
CONDITION
M
______________________________________________________________________________________
*
L
N
P
START
START CONDITION
A
0
0
1
1
1
A
0
1
0
1
2
*SEE ORDERING INFORMATION.
MSB
0
1
1
1
SLAVE ADDRESS BYTE
0
0
Slave Address
A
STOP CONDITION
1
LSB
A
2
SHDN
8
ACK
9
define a write or read protocol, sets the device’s power
mode (SHDN). The device is powered-down when
SHDN is set to one. During a device search routine, the
MAX5380/MAX5381/MAX5382 acknowledge both
options (SHDN = 0 or SHDN = 1), but do not change
their power state if a stop condition (or restart) is issued
immediately. The second byte (DAC data) must be
sent/received for the device to update both power
mode and DAC output.
The 8-bit DAC data is decoded as straight binary MSB
first with 1LSB = V
responding analog voltage as shown in Table 1. After
receiving the data byte, the devices acknowledge its
receipt and expect a STOP condition, at which point
the DAC output is updated.
The MAX5380/MAX5381/MAX5382 update the output
and the power mode only if the second byte is clocked
in (SHDN = 0) or out (SHDN = 1) of the device. When
SHDN = 1, the master will read all ones when clocking
out a data byte. The MAX5380/MAX5381/MAX5382 do
not drive SDA except for the acknowledge bit.
The MAX5380/MAX5381/MAX5382 are compatible with
existing I
ance inputs; SDA has an open drain that pulls the data
line low during the 9th clock pulse. Figure 7 shows a
typical I
supports standard I
eral call address is ignored, and CBUS formats are not
supported. The devices’ address is compatible with the
7-bit I 2 C addressing protocol only. No 10-bit formats
MSB
10
D7
D6
2
2
C application. The communication protocol
C systems. SCL and SDA are high-imped-
D5
D4
REF
DAC CODE
2
C 8-bit communications. The gen-
/ 256 and converted into the cor-
D3
D2
D1
I
2
C Compatibility
LSB
D0
17
DAC Data
18
ACK
CONDITION
STOP