PCM1604 BURR-BROWN [Burr-Brown Corporation], PCM1604 Datasheet
PCM1604
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PCM1604 Summary of contents
Page 1
... Sampling rates up to 200kHz are supported. A full set of user-programmable functions are accessible through a 4-wire serial control port which supports register write and readback functions. NOTE: (1) The PCM1604 and PCM1605 utilize the same die and are electrically identical. All references to the PCM1604 apply equally to the PCM1605. PDS-1564A ...
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... Full Scale (0dB) AC Load 5 0.002dB –3dB 0.546f S Stopband = 0.546f –75 S Stopband = 0.567f –82 S 0.002dB –3dB 0.732f S Stopband = 0.732f – 20kHz f = 44kHz 2 PCM1604Y, PCM1605Y TYP MAX UNITS 24 Bits 2 S, Left-Justified 16, 18, 20, 24-Bit 200 kHz S TTL-Compatible V 0 – 100 A –10 ...
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... NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “PCM1604Y/2K” will get a single 2000-piece Tape and Reel. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’ ...
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... ZERO4/GPO4 4 5 ZERO5/GPO5 ZERO6/GPO6 6 AGND OUT OUT OUT OUT ® PCM1604, PCM1605 DAC DAC 4x/8x Enhanced Oversampling DAC Multi-level Digital Filter Delta-Sigma with Modulator Function DAC Controller DAC DAC Zero Detect ...
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... Can also be used as GPO pin. OUT 6. Can also be used as GPO pin. OUT (3) (1) (1) (1) ( (2) S (1) (2) 1 and V 2 OUT OUT (2) 3 and V 4 OUT OUT (2) 5 and V 6 OUT OUT PCM1604, PCM1605 5 (2) or one-half of 128, 192, 256, 384, 512, S (2) . ® ...
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... Frequency (kHz) DE-EMPHASIS FREQUENCY RESPONSE (f 0 –2 –4 –6 –8 – Frequency (kHz) ® PCM1604, PCM1605 (f = 44.1kHz), and 24-bit input data, unless otherwise noted 44.1kHz) 0.003 0.002 0.001 0 –0.001 –0.002 –0.003 3 3 –2 – ...
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... 3.3V) 110 108 106 –60dB 104 102 100 98 0dB 96 5.5 6.0 4.0 = 3.3V) 110 108 106 104 102 S 100 98 96 5.5 6.0 4.0 7 DYNAMIC RANGE vs POWER SUPPLY (V = 3.3V) DD 44.1kHz, 384f S 96kHz, 384f S 4.5 5.0 5.5 V (V) CC CHANNEL SEPARATION vs POWER SUPPLY (V = 3.3V) DD 44.1kHz, 384f S 96kHz, 384f S 4.5 5.0 5.5 V (V) CC PCM1604, PCM1605 6.0 6.0 ® ...
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... V (V) CC SIGNAL-TO-NOISE RATIO vs POWER SUPPLY (V DD 110 108 106 192kHz-128f S 104 102 100 4 (V) CC ® PCM1604, PCM1605 (Cont.) = 3.3V) 110 108 S 106 104 102 100 5 3.3V) 110 108 106 104 102 100 and V 2) are operated ...
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... S 98 0dB 96 –25 75 100 CHANNEL SEPARATION vs TEMPERATURE 110 108 106 104 102 100 100 –25 PCM1604, PCM1605 9 DYNAMIC RANGE vs TEMPERATURE 44.1kHz, 384f S 96kHz, 384f 100 Temperature ( C) 44.1kHz, 384f S 96kHz, 384f 100 Temperature ( C) ...
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... SIGNAL-TO-NOISE RATIO vs TEMPERATURE 110 108 106 192kHz-128f S 104 102 100 98 96 –50 – Temperature ( C) ® PCM1604, PCM1605 (Cont.) system clock, 64x oversampling, and 24-bit data. Only two channels (V S 110 108 106 104 102 100 98 96 – 100 110 ...
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... DD enabled. The initialization sequence requires 1024 system clocks from the time V period, the PCM1604 will be set to its reset default state, as described in the Mode Control Register section of this data sheet. The PCM1604 also includes an external reset capability using the RST input (pin 37) ...
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... DATA1, DATA2 and DATA3 into the audio interface’s serial shift registers. Serial data is clocked into the PCM1604 on the rising edge of BCK. LRCK is the serial audio left/right word clock used to latch serial data into the serial audio interface’s internal registers ...
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... PCM1604, PCM1605 13 ® ...
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... Sixteen clocks are then provided on MC, corre- sponding to the 16-bits of the control data word on MDI. After the sixteenth clock cycle has completed set to logic ‘1’ to latch the data into the indexed mode control register. ® PCM1604, PCM1605 t t BCL LB ...
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... PCM1604, PCM1605 15 ® ...
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... NOTE: (1) MC rising edge for LSB to ML rising edge. FIGURE 10. Control Interface Timing. ® PCM1604, PCM1605 tion starts on the next HIGH to LOW transition of the ML pin. The Read cycle starts by setting the R/W bit of the control word to ‘1’, and setting all of the IDX[6:0] bits to ‘ ...
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... MODE CONTROL REGISTERS User-Programmable Mode Controls The PCM1604 includes a number of user-programmable functions which are accessed via control registers. The registers are programmed using the Serial Control Interface which was previously discussed in this data sheet. Table III lists the available mode control functions, along with their reset default conditions and associated register index ...
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... B 1111 1110 B 1111 1101 B • • • 1000 0010 B 1000 0001 B 1000 0000 B • • • 0000 0000 B ® PCM1604, PCM1605 B11 B10 IDX3 IDX2 IDX1 IDX0 AT17 IDX3 IDX2 IDX1 IDX0 AT27 IDX3 IDX2 IDX1 IDX0 AT37 ...
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... B11 B10 IDX3 IDX2 IDX1 IDX0 ATLD ATTS (default OUT 1 through V 6. The Soft Mute function is incorporated into the digital OUT OUT PCM1604, PCM1605 MUT6 MUT5 MUT4 MUT3 MUT2 MUT1 ® ...
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... DACx = 1 DAC Operation Disabled The DAC operation controls are used to enable and disable the DAC outputs, V DACx = 0, the output amplifier input is connected to the DAC output. When DACx = 1, the output amplifier input is switched to the DC common-mode voltage (V ® PCM1604, PCM1605 B11 B10 ...
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... The FMT[2:0] bits are used to select the data format for the serial audio interface. B11 B10 IDX3 IDX2 IDX1 IDX0 res res = f (default) SCKO SCKI = f /2 SCKO SCKI PCM1604, PCM1605 FLT0 CLKD CLKE FMT2 FMT1 FMT0 ® ...
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... This bit is Read/Write. Default Value: 0 REV = 0 Normal Output (non-inverted) REV = 1 Inverted Output The REV bit is used to invert the output phase for V detect functions (including zero-detect mute and the zero flags) are not available. ® PCM1604, PCM1605 B11 B10 IDX3 IDX2 ...
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... Refer to the Serial Control Interface section of this data sheet for details regarding the Single Register and Auto- Increment Read operations. B11 B10 IDX3 IDX2 IDX1 IDX0 INC REG6 PCM1604, PCM1605 REG5 REG4 REG3 REG2 REG1 REG0 . ...
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... The OVER bit is utilized to control the total oversampling performed by the D/A converter, including the digital interpolation filter and delta-sigma DAC. This is useful for controlling the D/A out-of-band noise spectrum, and designing a single, fixed value low-pass filter for use with all sampling frequencies. ® PCM1604, PCM1605 B11 B10 B9 ...
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... V 2 Pins. COM ZERO FLAG AND INFINITE ZERO DETECT MUTE FUNCTIONS The PCM1604 includes circuitry for detecting an all ‘0’ data condition for the data input pins, DATA1 through DATA3. This includes two independent functions: Zero Output Flags 1 through OUT and Zero Detect Mute ...
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... ZEROA 1 Zero- Output Flags or General- Purpose Outputs NOTE tantalum or aluminum electrolytic 0.1 F ceramic FIGURE 13. Basic Connection Diagram. ® PCM1604, PCM1605 PCM1604 PCM1605 ...
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... AGND2 CC 2 AGND1 CC 1 AGND0 MDO MDI MC ML FIGURE 14. Typical Application Diagram OUT 3 V OUT 4 V OUT 5 V OUT AGND ZERO6/GPO6 ZERO5/GPO5 ZERO4/GPO4 ZERO3/GPO3 ZERO2/GPO2 ZERO1/GPO1 PCM1604, PCM1605 ® ...
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... POWER SUPPLIES AND GROUNDING The PCM1604 requires a +5V analog supply and a +3.3V digital supply. The +5V supply is used to power the DAC analog and output filter circuitry, while the +3.3V supply is used to power the digital filter and serial interface circuitry. For best performance, the +3.3V supply should be derived from the +5V supply using a linear regulator, as shown in Figure 14 ...
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... Figure 17. A ground plane is recommended, with the analog and digital sections being isolated from one another using a split or cut in the circuit board. The PCM1604 or PCM1605 should be oriented with the digital I/O pins facing the ground plane split/cut to allow for short, direct connections to the digital audio interface and control signals originating from the digital section of the board ...
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... THEORY OF OPERATION The D/A converter section of the PCM1604 is based upon a multi-bit delta-sigma architecture. This architecture utilizes -order noise shaper and an 8-level quantizer, followed by an analog low-pass filter. A block diagram of the delta-sigma modulator is shown in Figure 19. This architecture has the advantage of stability and improved jitter tolerance when compared to traditional 1-bit (2-level) delta-sigma designs ...
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... Required for THD+N test. FIGURE 22. Test Setup for THD+N Measurements. For the PCM1604 and PCM1605 D/A converters, THD+N is measured with a full scale, 1kHz digital sine wave as the test stimulus at the input of the DAC. The digital generator is set to 24-bit audio word length and a sampling frequency of 44 ...
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... The SNR test provides a measure of the noise floor of the D/A converter. The input to the D/A is all 0’s data, and the D/A converter’s Infinite Zero Detect Mute function must be disabled (default condition at power up for the PCM1604, PCM1605). This ensures that the delta-sigma modulator output is connected to the output amplifier circuit so that idle tones (if present) can be observed and effect the SNR measurement ...