MAX5980 MAXIM [Maxim Integrated Products], MAX5980 Datasheet
MAX5980
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MAX5980 Summary of contents
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... Rev 1; 9/11 Quad, IEEE 802.3at/af PSE Controller General Description The MAX5980 is a quad, power-sourcing equipment (PSE) power controller designed for use in IEEE 802.3at/af-compliant PSE. This device provides powered device (PD) discovery, classification, current limit, and load disconnect detection. The device supports both fully automatic operation and software programmability ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet ABSOLUTE MAXIMUM RATINGS (Voltages referenced unless otherwise noted.) EE AGND ....................................................................-0.3V to +80V DGND, SVEE_ ......................................................-0.3V to +0.3V V ........................ -0.3V to the lower (V DD OUT_ ....................................................-0. ...
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Quad, IEEE 802.3at/af PSE Controller ELECTRICAL CHARACTERISTICS (continued 32V to 60V 0V, T AGND EE DGND values are 54V +25NC, and default register settings. Currents are positive when entering ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet ELECTRICAL CHARACTERISTICS (continued 32V to 60V 0V, T AGND EE DGND values are 54V +25NC, and default register settings. Currents are positive ...
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Quad, IEEE 802.3at/af PSE Controller ELECTRICAL CHARACTERISTICS (continued 32V to 60V 0V, T AGND EE DGND values are 54V +25NC, and default register settings. Currents are positive when entering ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet ELECTRICAL CHARACTERISTICS (continued 32V to 60V 0V, T AGND EE DGND values are 54V +25NC, and default register settings. Currents are positive ...
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Quad, IEEE 802.3at/af PSE Controller (V = 32V to 60V 0V, T AGND EE DGND values are 54V +25NC, ENDPOINT mode, and default register settings with a Class 0 PD, unless ...
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... I OUT_ 200mA /div V GATE_ 10V/div 20ms/div (R = 240I TO 75I) LOAD MAX5980 toc11 AGND OUT_ 50V/div I OUT_ 200mA /div V GATE_ 10V/div 400µs/div OUTPUT SHORT-CIRCUIT RESPONSE TIME MAX5980 toc13 AGND OUT_ 20V/div I OUT_ 10A /div V GATE_ 10V/div 10µs/div ...
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... Typical EE ZERO CURRENT DETECTION MAX5980 toc15 V 20V/div 0V I OUT_ 100mA/div V 10V/div 0V 100ms/div STARTUP WITH VALID PD (25kI, 0.1µF, CLASS 3) MAX5980 toc17 V AGND 20V/div I OUT_ 200mA/div V GATE_ 10V/div 100ms/div DETECTION WITH INVALID PD (33kI AND 0.1µF) MAX5980 toc18b V AGND 5V/div ...
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... OUT_ 20V/div 0V I OUT_ 200mA/div V GATE_ 0mA 10V/div , unless otherwise noted. Typical EE DETECTION WITH INVALID PD (OPEN CIRCUIT) MAX5980 toc18d AGND OUT_ 5V/div I OUT_ 1mA/div V GATE_ 10V/div 100ms/div INVALID PD (15kI AND 0.1µF) MAX5980 toc20a AGND OUT_ 5V/div I OUT_ 1mA/div 400ms/div ...
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... AGND OUT_ 10V/div 0V I OUT_ 10mA/div 0mA , unless otherwise noted. Typical EE DETECTION WITH OUT_ SHORTED TO AGND MAX5980 toc21 AGND OUT_ 5V/div I OUT_ 1mA/div V GATE_ 10V/div 40ms/div 4 AND 5 PDs MAX5980 toc23 AGND OUT_ 10V/div CLASS 5 CLASS 4 I OUT_ 20mA/div 40ms/div 11 ...
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... DGND Digital Low-Side Supply Input. Connect to V Port 3/4 Current-Sense Negative Terminal Input. Use Kelvin-sensing technique in PCB layout for best 10 SVEE2 accuracy current sensing N.C. 28 MAX5980 *EP + INT TQFN EE FUNCTION DD . Leave them unconnected to use the default device address DD externally ...
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Quad, IEEE 802.3at/af PSE Controller PIN NAME Analog Low-Side Supply Input. Bypass with an external 100V, 0.1FF ceramic capacitor between AGND and V Digital High-Side Supply Output. Bypass with an external RC network; see the V 12 ...
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... EN VOLTAGE PROBING AND CURRENT-LIMIT CONTROL DETECTION AND PORT STATE CLASSIFICATION MACHINE (SM) CONTROL POWER ENABLE GATE-DRIVE CONTROL FAST DISCHARGE MAX5980 CURRENT LIMIT, OVERCURRENT, AND OPEN-CIRCUIT SENSING, AND FOLDBACK CONTROL THRESHOLD SETTINGS SVEE1 SVEE2 Functional Diagram OUT_ CURRENT SENSING VOLTAGE 9-BIT ADC ...
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... Quad, IEEE 802.3at/af PSE Controller Detailed Description The MAX5980 is a quad PSE power controller designed for use in IEEE 802.3at/af-compliant PSE. This device provides PD discovery, classification, current limit, and load disconnect detections. The device supports both fully automatic operation and software programmability. ...
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... Table 19) to [10]. When entering semi mode, the DET_EN_ and CLASS_EN_ bits retain their previous states. When the DET_EN_ and/or CLASS_EN_ bits are set to 1, the MAX5980 performs detection and/or classification repeatedly, but do not power up the port(s) automatically. Setting R19h[3:0] (PWR_ON_, Table 26) high turns on power to the port(s) if detection and classification has successfully completed ...
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Quad, IEEE 802.3at/af PSE Controller To prevent damage to non-PD devices, and to protect itself from an output short circuit, the device limits the current into OUT_ to less than 2mA (max) during PD detection. In midspan mode, after every ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet 80ms 150ms t 0V -4V -9.1V -18V -54V OUT_ AGND Figure 1. Detection, Classification, and Port Power-Up Sequence 2-Event PD Classification If the result of the first classification event is ...
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Quad, IEEE 802.3at/af PSE Controller 80ms 150ms t DET(1) 0V -4V -9.1V -18V -54V OUT_ AGND Figure 2. Detection, 2-Event Classification, and Port Power-Up Sequence V exceeds V and decreases at a slower RSENSE_ CUT pace when ...
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... INT is asserted low (unless masked). If the master device on the I to turn off the EE Response Address, any MAX5980 device on the bus that has INT asserted will respond (see the Global Addressing and the Alert Response Address (ARA) section response to an interrupt, the controller can read the status of the event register(s) to determine the cause of the interrupt and take appropriate action ...
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... MAX5980 Figure 4. V External Power Sourcing DD for Power-over-Ethernet load shared among multiple MAX5980 devices, isolate the external supply bus with a series resistor (50I for 3 devices, 75I for 4 devices), and place a single 1FF capacitor on the bus. EE The EN digital input is referenced to DGND and is used exceeds 28 ...
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... Device Address (AD0) The MAX5980 is programmable unique slave device addresses. The three MSBs of the device address are always [010]. The 4 LSBs of the device address are programmable, and are formed by the states of the Slave Address Inputs (A0, A1, A2, and A3; see Table 3). To ...
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... SDA during the acknowledge clock pulse, so the SDA line is stable low during the high period of the clock pulse. When the master transmits to the MAX5980, the device generates the acknowledge bit. When the device transmits to the master, the master Bit Transfer generates the acknowledge bit ...
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... The actual alert response address (ARA) is 0Ch. The MAX5980 slave device only responds to the ARA if its INT (interrupt) output is asserted. All MAX5980 devices in which the INT output is not asserted ignore the ARA. ...
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... When performing read-after-write verification, remember to reset the command byte’s address because the stored control byte address auto- increments after the write. ACKNOWLEDGE FROM THE MAX5980 ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Operation with Multiple Masters When the device operates on a 3-wire interface with mul- tiple masters, a master reading the device should use repeated starts between the write that sets the device’s address ...
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Quad, IEEE 802.3at/af PSE Controller Table 5. Register Map Summary (continued) REGISTER ADDR TYPE BIT 7 NAME STATUS 0Ch Port 1 Status R — 0Dh Port 2 Status R — 0Eh Port 3 Status R — 0Fh Port 4 Status ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Table 5. Register Map Summary (continued) REGISTER ADDR TYPE BIT 7 NAME MAXIM RESERVED 20h Reserved — — 21h Reserved — — 22h Reserved — — 23h Reserved — — 24h Reserved — ...
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Quad, IEEE 802.3at/af PSE Controller Table 5. Register Map Summary (continued) REGISTER ADDR TYPE BIT 7 NAME Developer 43h ID/Revision R/W DEV_ID[2] Number High-Power 44h R/W — Enable 45h Reserved —- — 46h Port 1 GPMD R/W — 47h Port ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Register Map and Description The device contains a bank of volatile registers that store its settings and status. The device features an I compatible, 3-wire serial interface, allowing the registers to be fully ...
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Quad, IEEE 802.3at/af PSE Controller Interrupt Mask Register (R01h) The Interrupt Mask register (R01h, Table 7) contains mask bits that suppress the corresponding interrupt bits in register R00h (active-high). Setting mask bits low individually disables the corresponding interrupt signal. When ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Detect Event Register (R04h/R05h) The Detect Event register (R04h/R05h, Table 9) records detection/classification events for the port. On power-up or after a reset condition, the Detect Event register is set to a default ...
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Quad, IEEE 802.3at/af PSE Controller Startup Event Register (R08h/R09h) The Startup Event register (R08h/R09h, Table 11) records port startup failure events and current-limit disconnect timeout events. On power-up or after a reset condition, the Fault Event register is set to ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Status Registers (R0Ch–R11h) Port Status Registers (R0Ch–R0Fh) The Port Status registers (R0Ch–R0Fh, Table 13) record the results of the port detection and classification at the end of each phase in three encoded bits. ...
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Quad, IEEE 802.3at/af PSE Controller Power Status Register (R10h) The Power Status register (R10h, Table 16) records the current status of port power. On power-up or after a reset condition, the port is initially unpowered and the Power Status register ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Configuration Registers (R12h–R17h) Operating Mode Register (R12h) The Operating Mode register in the device (R12h, Table 19) contains 2 bits per port that set the port mode of operation. Table 20 details how ...
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Quad, IEEE 802.3at/af PSE Controller Detection and Classification Enable Register (R14h) The Detection and Classification Enable register (R14h, Table 22) is used to enable detection and classification routines for the ports power-up or after a reset con- dition, ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Miscellaneous Configuration 1 Register (R17h) The Miscellaneous Configuration 1 register (R17h, Table 24) is used for several functions that do not cleanly fit within one of the other configuration catego- ries ...
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Quad, IEEE 802.3at/af PSE Controller Pushbutton Registers (R18h–R1Ah) Detection/Classification Pushbutton Register (R18h) The Detection/Classification Pushbutton register (R18h, Table 25) is used as a pushbutton to set the corre- sponding bits in the Detection and Classification Enable register (R14h, Table 22). ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet General Registers (R1Bh–R1Fh) The ID register (R1Bh, Table 28) keeps track of the device ID number and revision. The device’s ID code is stored in ID_CODE[4:0] (R1Bh[7:3]) and is 11010. Contact the factory ...
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Quad, IEEE 802.3at/af PSE Controller TLIM Programming Registers (R1Eh and R1Fh) The TLIM Programming registers (R1Eh/R1Fh, Table 30) are used to adjust the t current-limit timeout duration. LIM On a power-up or after a reset condition, this register is set ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Current/Voltage Readout Registers Port Current Registers (R30h, R31h, R34h, R35h, R38h, R39h, and R3Ch, R3Dh) The Port Current registers (Tables 32 and 33) provide port current readout when a port is powered on. ...
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Quad, IEEE 802.3at/af PSE Controller Port Voltage Registers (R32h, R33h, R36h, R37h, R3Ah, R3Bh, R3Eh, and R3Fh) The Port Voltage registers (Tables 34 and 35) provide port voltage readout when a port is powered on power-up or after ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Other Functions Registers (R00h, R01h) Reserved Registers (R40h, R45h, R4Ah, R4Fh, R54h, R59h, R5Ah, R5Bh, R5Ch, R5Dh, R5Eh, R5Fh) These registers are at this time reserved. Writing to these registers will have no ...
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Quad, IEEE 802.3at/af PSE Controller High-Power Enable Register (R44h) The High-Power Enable register (R44h, Table 38) is used to enable the high-power features on the ports. On power-up or after a reset condition, if AUTO = 1, this register is ...
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Quad, IEEE 802.3at/af PSE Controller for Power-over-Ethernet Port Current-Limit Register (R48h, R4Dh, R52h, and R57h) The Port Current-Limit registers (Table 41) are used to set the current-limit SENSE_ voltage threshold for the corre- sponding port power-up or after ...
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... EE 4) Use short, wide traces whenever possible for high- power paths. 5) Use the MAX5980 Evaluation Kit as a design and layout reference. 6) The exposed pad (EP) must be soldered evenly to the PCB ground plane (V and power dissipation. Use multiple vias beneath the exposed pad for maximum heat dissipation ...
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... PROCESS: CMOS 48 0.1µF INTERNAL PULLUP 100V AGND -54V V DD 1.8kI OUT1 -54V GATE1 3kI SENSE1 OUT2 SDAOUT GATE2 3kI MAX5980 SDAIN SENSE2 OUT3 3kI GATE3 SCL SENSE3 3kI INT OUT4 EN GATE4 AUTO DD MIDSPAN DD SENSE4 EN_CL5 DGND V SVEE1 SVEE2 EE ...
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Quad, IEEE 802.3at/af PSE Controller REVISION REVISION NUMBER DATE 0 12/10 Initial release Globally changed operating temperature range to -40°C to +105°C throughout 1 8/11 data sheet. Added conditions to Offset Error and Gain Error in the Electrical Characteristics Table. ...