AD6655-125EBZ1 AD [Analog Devices], AD6655-125EBZ1 Datasheet - Page 57

• Manufacturer Part Number: AD6655-125EBZ1
• Description: IF Diversity Receiver
• Manufacturer: AD [Analog Devices]

Signal Monitor DC Value Channel B (Register 0x10F and
Register 0x110)
Register 0x110, Bits[7:6]—Reserved
Register 0x110, Bits[5:0]—Channel B DC Value Bits[13:8]
Register 0x10F, Bits[7:0]—Channel B DC Value Bits [7:0]
These read-only registers hold the latest dc offset value computed
by the signal monitor for Channel B.
Signal Monitor SPORT Control (Register 0x111)
Bit 7—Reserved
Bit 6—RMS/MS Magnitude Output Enable
Bit 6 enables the 20-bit rms or ms magnitude measurement as
output on the SPORT.
Bit 5—Peak Detector Output Enable
Bit 5 enables the 13-bit peak measurement as output on the SPORT.
Bit 4—Threshold Crossing Output Enable
Bit 4 enables the 13-bit threshold measurement as output on the
SPORT.
Bits[3:2]—SPORT SMI SCLK Divide
The values of these bits set the SPORT SMI SCLK divide ratio from
the input clock. A value of 0x01 sets divide by 2 (default), a value
of 0x10 sets divide by 4, and a value of 0x11 sets divide by 8.
Bit 1—SPORT SMI SCLK Sleep
Setting Bit 1 high causes the SMI SCLK to remain low when the
signal monitor block has no data to transfer.
Bit 0—Signal Monitor SPORT Output Enable
When set, Bit 0 enables the signal monitor SPORT output to
begin shifting out the result data from the signal monitor block.
Signal Monitor Control (Register 0x112)
Bit 7—Complex Power Calculation Mode Enable
This mode assumes I data is present on one channel and Q data
is present on the alternate channel. The result reported is the
complex power measured as
Bits[6:4]—Reserved
Bit 3—Signal Monitor RMS/MS Select
Setting Bit 3 low selects rms power measurement mode. Setting
Bit 3 high selects ms power measurement mode.
Bits[2:1]—Signal Monitor Mode
Bit 2 and Bit 1 set the mode of the signal monitor for data
output to registers at Address 0x116 through Address 0x11B.
Setting these bits to 0x00 selects rms/ms magnitude output,
setting these bits to 0x01 selects peak detector output, and
setting 0x10 or 0x11 selects threshold crossing output.
I +
2
Q
2
Rev. 0 | Page 57 of 84
Bit 0—Signal Monitor Enable
Setting Bit 0 high enables the signal monitor block.
Signal Monitor Period (Register 0x113 to Register 0x115)
Register 0x115 Bits[7:0]—Signal Monitor Period[23:16]
Register 0x114 Bits[7:0]—Signal Monitor Period[15:8]
Register 0x113 Bits[7:0]—Signal Monitor Period[7:0]
This 24-bit value sets the number of clock cycles over which the
signal monitor performs its operation. The minimum value for
this register is 128 cycles (programmed values less than 128
revert to 128).
Signal Monitor Result Channel A (Register 0x116 to
Register 0x118)
Register 0x118, Bits[7:4]—Reserved
Register 0x118, Bits[3:0]—Signal Monitor Result
Channel A[19:16]
Register 0x117, Bits[7:0]—Signal Monitor Result
Channel A[15:8]
Register 0x116, Bits[7:0]—Signal Monitor Result
Channel A[7:0]
This 20-bit value contains the power value calculated by the
signal monitor block for Channel A. The content is dependent
on the settings in Register 0x112, Bits[2:1].
Signal Monitor Result Channel B (Register 0x119 to
Register 0x11B)
Register 0x11B, Bits[7:4]—Reserved
Register 0x11B, Bits[3:0]—Signal Monitor Result
Channel B[19:16]
Register 0x11A, Bits[7:0]—Signal Monitor Result
Channel B[15:8]
Register 0x119, Bits[7:0]—Signal Monitor Result
Channel B[7:0]
This 20-bit value contains the power value calculated by the
signal monitor block for Channel B. The content is dependent
on the settings in Register 0x112, Bits[2:1].
NCO Control (Register 0x11D)
Bits[7:3]—Reserved
Bit 2—NCO32 Phase Dither Enable
When Bit 2 is set, phase dither in the NCO is enabled. When
Bit 2 is cleared, phase dither is disabled.
Bit 1—NCO32 Amplitude Dither Enable
When Bit 1 is set, amplitude dither in the NCO is enabled.
When Bit 1 is cleared, amplitude dither is disabled.
AD6655