MAX691A MAXIM [Maxim Integrated Products], MAX691A Datasheet - Page 7

• Manufacturer Part Number: MAX691A
• Description: Microprocessor Supervisory Circuits
• Manufacturer: MAXIM [Maxim Integrated Products]

The MAX691A/MAX693A/MAX800L/MAX800M’s RESET
and RESET outputs ensure that the µP (with reset
inputs asserted either high or low) powers up in a
known state, and prevents code-execution errors dur-
ing power-down or brownout conditions.
The RESET output is active low, and typically sinks
3.2mA at 0.1V saturation voltage in its active state.
When deasserted,
V
and typically sinks 3.2mA with a saturation voltage of
0.1V. When no backup battery is used, RESET output is
______________________________________________________________Pin Description
_______________Detailed Description
PIN
OUT
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
- 0.5V. RESET output is open drain, active high,
LOW LINE LOW LINE output goes low when V
BATT ON
OSC SEL
CE OUT
OSC IN
RESET
RESET
NAME
VBATT
CE IN
V
WDO
GND
PFO
V
WDI
PFI
OUT
CC
Battery-Backup Input. Connect to external battery or capacitor and charging circuit. If backup battery is not
used, connect to GND.
Output Supply Voltage. When V
V
capacitor from V
Input Supply Voltage, 5V input.
Ground. 0V reference for all signals.
Battery On Output. When V
goes low. Connect the base of a PNP through a current-limiting resistor to BATT ON for V
ments greater than 250mA.
the reset threshold.
External Oscillator Input. When OSC SEL is unconnected or driven high, a 10µA pull-up connects from V
OSC IN, the internal oscillator sets the reset and watchdog timeout periods, and OSC IN selects between fast
and slow watchdog timeout periods. When OSC SEL is driven low, the reset and watchdog timeout periods may
be set either by a capacitor from OSC IN to ground or by an external clock at OSC IN (Figure 3).
Oscillator Select. When OSC SEL is unconnected or driven high, the internal oscillator sets the reset delay and
watchdog timeout period. When OSC SEL is low, the external oscillator input (OSC IN) is enabled (Table 1).
OSC SEL has a 10µA internal pull-up.
Power-Fail Input. This is the noninverting input to the power-fail comparator. When PFI is less than 1.25V, PFO
goes low. When PFI is not used, connect PFI to GND or V
Power-Fail Output. This is the output of the power-fail comparator. PFO goes low when PFI is less than 1.25V.
This is an uncommitted comparator, and has no effect on any other internal circuitry.
Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than the watchdog time-
out period, WDO goes low and reset is asserted for the reset timeout period. WDO remains low until the next tran-
sition at WDI. Leaving WDI unconnected disables the watchdog function. WDI connects to an internal voltage
divider between V
Chip-Enable Output. CE OUT goes low only when CE IN is low and V
low when reset is asserted, CE OUT will stay low for 15µs or until CE IN goes high, whichever occurs first.
Chip-Enable Input. The input to chip-enable gating circuit. If CE IN is not used, connect CE IN to GND or V
Watchdog Output. If WDI remains high or low longer than the watchdog timeout period, WDO goes low and reset
is asserted for the reset timeout period. WDO returns high on the next transition at WDI. WDO remains high if
WDI is unconnected.
RESET Output goes low whenever V
200ms after V
RESET is an active-high output. It is open drain, and the inverse of RESET.
_______________________________________________________________________________________
CC
–
RESET sources 1.6mA at typically
–
R
—
. When V
E
—
S
—
E
—
Microprocessor Supervisory Circuits
T
–
CC
CC
and RESET Outputs
OUT
falls below VBATT and is below the reset threshold, V
crosses the reset threshold on power-up.
OUT
to GND. Connect V
and GND, which sets it to mid-supply when left unconnected.
OUT
switches to VBATT, BATT ON goes high. When V
CC
CC
is greater than VBATT and above the reset threshold, V
CC
falls below the reset threshold. It returns high as soon as V
falls below the reset threshold. RESET will remain low typically for
OUT
to V
guaranteed to be valid down to V
external 10kΩ pull-down resistor on RESET insures
that it will be valid with V
As V
output switch reduces accordingly, increasing the
R
down resistor insures the parallel combination of switch
plus resistor is around 10kΩ and the output saturation
voltage is below 0.4V while sinking 40µA. When using
a 10kΩ external pull-down resistor, the high state for
RESET output with V
For battery voltages ≥ 2V connected to VBATT, RESET
and RESET remain valid for V
CC
FUNCTION
DS(ON)
if no backup battery is used.
CC
OUT
goes below 1V, the gate drive to the RESET
and the saturation voltage. The 10kΩ pull-
.
CC
OUT
is above the reset threshold. If CE IN is
CC
connects to VBATT. Connect a 0.1µF
= 4.75V will be 4.5V typical.
CC
OUT
CC
down to GND (Figure 1).
switches to V
from 0V to 5.5V.
OUT
OUT
CC
current require-
connects to
= 1V, and an
CC
CC,
rises above
BATT ON
OUT
OUT.
to
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