MAX6948B MAXIM [Maxim Integrated Products], MAX6948B Datasheet - Page 22

• Manufacturer Part Number: MAX6948B
• Description: High-Efficiency PWM LED Driver with Boost Converter and Five Constant-Current GPIO Ports
• Manufacturer: MAXIM [Maxim Integrated Products]

Figure 8. 2-Wire Serial-Interface Timing Details
Figure 9. START and STOP Conditions
High-Efficiency PWM LED Driver with Boost
Converter and Five Constant-Current GPIO Ports
Figure 8 shows the 2-wire serial-interface timing details.
The MAX6948B operates as a slave that sends and
receives data through an I
face. The interface uses a serial-data line (SDA) and
a serial-clock line (SCL) to achieve bidirectional com-
munication between master(s) and slave(s). A master
(typically a microcontroller) initiates all data transfers to
and from the MAX6948B and generates the SCL clock
that synchronizes the data transfer.
The MAX6948B’s SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7kI, is
required on SDA. The MAX6948B’s SCL line operates only
as an input. A pullup resistor is required on SCL if there are
multiple masters on the 2-wire interface, or if the master in a
single-master system has an open-drain SCL output.
22
SDA
SCL
CONDITION
START
S
SCL
SDA
t
HD , STA
START CONDITION
t
LOW
2
C-compatible 2-wire inter-
t
R
Serial Interface
t
SU, DAT
t
HIGH
Serial Addressing
t
F
t
HD, DAT
CONDITION
STOP
P
t
SU, STA
REPEATED START CONDITION
Figure 10. Bit Transfer
Each transmission consists of a START condition (Figure
9) sent by a master, followed by the MAX6948B 7-bit
slave address plus R/W bit, a register address byte, 1 or
more data bytes, and finally a STOP condition.
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START (S) condition by transitioning SDA from high
to low while SCL is high. When the master has finished
communicating with the slave, it issues a STOP (P) con-
dition by transitioning SDA from low to high while SCL is
high. The bus is then free for another transmission.
One data bit is transferred during each clock pulse
(Figure 10). The data on SDA must remain stable while
SCL is high.
SDA
SCL
t
HD, STA
DATA LINE STABLE;
DATA VALID
START and STOP Conditions
CHANGE OF DATA
ALLOWED
t
SU, STO
CONDITION
STOP
t
BUF
Bit Transfer
CONDITION
START