LM12H458MEL/883 NSC [National Semiconductor], LM12H458MEL/883 Datasheet - Page 28

• Manufacturer Part Number: LM12H458MEL/883
• Description: 12-Bit Sign Data Acquisition System with Self-Calibration
• Manufacturer: NSC [National Semiconductor]

www.national.com
2.0 Internal User-Programmable
Registers
The
self-calibration generates Interrupt 4.
Interrupt 5 is generated when the Sequencer encounters an
instruction that has its Pause bit (Bit 1 in Instruction RAM
“00”) set to “1”.
The LM12(H)454/8 issues Interrupt 6 whenever it senses
that its power supply voltage is dropping below 4V (typ). This
interrupt indicates the potential corruption of data returned
by the LM12(H)454/8.
Interrupt 7 is issued after a short delay (10 ms typ) while the
LM12(H)454/8 returns from Standby mode to active opera-
tion using the Configuration register’s Bit 4. This short delay
allows the internal analog circuitry to settle sufficiently, en-
suring accurate conversion results.
2.4 INTERRUPT ENABLE REGISTER
The Interrupt Enable register at address location 1001
(A4–A1, BW = 0) or 1001x (A4–A0, BW = 1) has READ/
WRITE capability. An individual interrupt’s ability to produce
an external interrupt at pin 31 (INT) is accomplished by plac-
ing a “1” in the appropriate bit location. Any of the internal
interrupt-producing operations will set their corresponding
bits to “1” in the Interrupt Status register regardless of the
state of the associated bit in the Interrupt Enable register.
See Section 2.3 for more information about each of the eight
internal interrupts.
Bit 0 enables an external interrupt when an internal “watch-
dog” comparison limit interrupt has taken place.
Bit 1 enables an external interrupt when the Sequencer has
reached the address stored in Bits 8–10 of the Interrupt En-
able register.
Bit 2 enables an external interrupt when the Conversion
FIFO’s limit, stored in Bits 11–15 of the Interrupt Enable reg-
ister, has been reached.
Bit 3 enables an external interrupt when the single-sampled
auto-zero calibration has been completed.
Bit 4 enables an external interrupt when a full auto-zero and
linearity self-calibration has been completed.
Bit 5 enables an external interrupt when an internal Pause
interrupt has been generated.
Bit 6 enables an external interrupt when a low power supply
condition (V
Bit 7 enables an external interrupt when the LM12(H)454/8
return from power-down to active mode.
Bits
user-programmable value against which the Sequencer’s
address is compared. When the Sequencer reaches an ad-
dress that is equal to the value stored in Bits 8–10, an inter-
nal interrupt is generated and appears in Bit 1 of the Interrupt
Status register. If Bit 1 of the Interrupt Enable register is set
to “1”, an external interrupt will appear at pin 31 (INT).
The value stored in bits 8–10 ranges from 000 to 111, repre-
senting 0 to 7 instructions stored in the Instruction RAM. Af-
ter the Instruction RAM has been programmed and the RE-
SET bit is set to “1”, the Sequencer is started by placing a “1”
in the Configuration register’s START bit. Setting the INT 1
trigger value to 000 does not generate an INT 1 the first
time the Sequencer retrieves and decodes Instruction 000.
The Sequencer generates INT 1 (by placing a “1” in the In-
terrupt Status register’s Bit 1) the second time and after the
Sequencer encounters Instruction 000. It is important to re-
completion
8–10
A
+
<
form
(Continued)
4V) has generated an internal interrupt.
of
the
a
full
storage
auto-zero
location
and
of
linearity
the
28
member that the Sequencer continues to operate even if an
Instruction interrupt (INT 1) is internally or externally gener-
ated. The only mechanisms that stop the Sequencer are an
instruction with the PAUSE bit set to “1” (halts before instruc-
tion execution), placing a “0” in the Configuration register’s
START bit, or placing a “1” in the Configuration register’s RE-
SET bit.
Bits 11–15 hold the number of conversions that must be
stored in the Conversion FIFO in order to generate an inter-
nal interrupt. This internal interrupt appears in Bit 2 of the In-
terrupt Status register. If Bit 2 of the Interrupt Enable register
is set to “1”, an external interrupt will appear at pin 31 (INT).
2.5 INTERRUPT STATUS REGISTER
This read-only register is located at address 1010 (A4–A1,
BW = 0) or 1010x (A4–A0, BW = 1). The corresponding flag
in the Interrupt Status register goes high (“1”) any time that
an interrupt condition takes place, whether an interrupt is en-
abled or disabled in the Interrupt Enable register. Any of the
active (“1”) Interrupt Status register flags are reset to “0”
whenever this register is read or a device reset is issued
(see Bit 1 in the Configuration Register).
Bit 0 is set to “1” when a “watchdog” comparison limit inter-
rupt has taken place.
Bit 1 is set to “1” when the Sequencer has reached the ad-
dress stored in Bits 8–10 of the Interrupt Enable register.
Bit 2 is set to “1” when the Conversion FIFO’s limit, stored in
Bits 11–15 of the Interrupt Enable register, has been
reached.
Bit 3 is set to “1” when the single-sampled auto-zero has
been completed.
Bit 4 is set to “1” when an auto-zero and full linearity
self-calibration has been completed.
Bit 5 is set to “1” when a Pause interrupt has been gener-
ated.
Bit 6 is set to “1” when a low-supply voltage condition
(V
Bit 7 is set to “1” when the LM12(H)454/8 return from
power-down to active mode.
Bits 8–10 hold the Sequencer’s actual instruction address
while it is running.
Bits 11–15 hold the actual number of conversions stored in
the Conversion FIFO while the Sequencer is running.
2.6 LIMIT STATUS REGISTER
The read-only register is located at address 1101 (A4–A1,
BW = 0) or 1101x (A4–A0, BW = 1). This register is used in
tandem with the Limit # 1 and Limit # 2 registers in the Instruc-
tion RAM. Whenever a given instruction’s input voltage ex-
ceeds the limit set in its corresponding Limit register ( # 1 or
# 2), a bit, corresponding to the instruction number, is set in
the Limit Status register. Any of the active (“1”) Limit Status
flags are reset to “0” whenever this register is read or a de-
vice reset is issued (see Bit 1 in the Configuration register).
This register holds the status of limits # 1 and # 2 for each of
the eight instructions.
Bits 0–7 show the Limit # 1 status. Each bit will be set high
(“1”) when the corresponding instruction’s input voltage ex-
ceeds the threshold stored in the instruction’s Limit # 1 regis-
ter. When, for example, instruction 3 is a “watchdog” opera-
tion (Bit 11 is set high) and the input for instruction 3 meets
the magnitude and/or polarity data stored in instruction 3’s
Limit # 1 register, Bit 3 in the Limit Status register will be set
to a “1”.
A
+
<
4V) has taken place.