DAC729JH BURR-BROWN [Burr-Brown Corporation], DAC729JH Datasheet - Page 6

• Manufacturer Part Number: DAC729JH
• Description: Ultra-High Resolution 18-BIT DIGITAL-TO-ANALOG CONVERTER
• Manufacturer: BURR-BROWN [Burr-Brown Corporation]

ACCURACY
Linearity
This specification describes one of the most important mea-
sures of performance of a D/A converter. Linearity error is
the deviation of the analog output versus code transfer
function from a straight line drawn through the end points
(all bits ON point and all bits OFF point).
Differential Linearity Error
Differential Linearity Error (DLE) of a D/A converter is the
deviation from an ideal 1LSB change in the output from one
adjacent output state to the next. A differential linearity error
specification of 1/2LSB means that the output step sizes
can be between 1/2 LSB and 3/2LSB when the input changes
from one adjacent input state to the next. A negative DLE
specification of no more than –1LSB (–0.0015% for 16-bit
resolution) insures monotonicity to 16 bits.
Monotonicity
Monotonicity assures that the analog output will increase or
remain the same for increasing input digital codes. The
DAC729KH is specified to be monotonic to 16 bits over the
entire specification temperature range.
DRIFT
Gain Drift
Gain drift is a measure of the change in the full-scale range
output over temperature expressed in parts per million per
degree centigrade (ppm/ C). Gain drift is measured by: (1)
testing the end point differences for each D/A at t
and t
+25 C value; and (3) dividing by the temperature change.
Offset Drift
Offset drift is a measure of the change in the output with
3FFFF
temperature range. The maximum change in offset at t
t
by the temperature change. This drift is expressed in parts
per million of full-scale range per degree centigrade (ppm of
FSR/ C).
SETTLING TIME
Settling time of the D/A is the total time required for the
analog output to settle within an error band around its final
value after a change in digital input. Settling time includes
the slew time of the op amp.
Voltage Output
Settling times are specified to 0.00076% of FSR scale
range change of 20V (COB) or 10V (CSB) and a 1LSB
change at the “major carry,” the point at which the worst-
case settling time occurs. (This is the worst-case point since
all of the input bits change when going from one code to the
next.)
Current Output
Settling times are specified to 0.00076% of FSR for a full-
scale range change with an output load resistance of 10 .
MAX
is referenced to the offset error at +25 C and is divided
MAX
H
; (2) calculating the gain error with respect to the
applied to the digital inputs over the specified
DAC729
MIN
, +25 C,
MIN
or
6
COMPLIANCE VOLTAGE
Compliance voltage applies only to the current output mode
of operation. It is the maximum voltage swing allowed on
the output current pin while still being able to maintain
specified linearity.
POWER SUPPLY SENSITIVITY
Power supply sensitivity is a measure of the effect of a
change in a power supply voltage on the D/A converter full-
scale output. It is defined as a percent of FSR change in the
output per percent of change in either the positive supply
(+V
the nominal power supply voltages (see Figure 1). It is
specified for DC or low frequency changes. The typical
performance curve in Figure 1 shows the effect of high
frequency changes in power supply voltages using internal
reference, DAC, and op amp.
FIGURE 1. Power Supply Sensitivity vs Frequency Using
OPERATING INSTRUCTIONS
POWER SUPPLY CONNECTIONS
For optimum performance and noise rejection, power supply
decoupling capacitors should be added as shown in Figure 2.
These capacitors (1 F to 10 F tantalum recommended)
should be located at the DAC729.
EXTERNAL OFFSET AND GAIN ADJUSTMENT
Offset and gain may be trimmed by installing external offset
and gain potentiometers. Connect these potentiometers as
shown in Figure 3 and adjust as described below. TCR of
the potentiometers should be 100ppm/ C or less. The 3.9M
and 510k
located close to the DAC729 to prevent noise pickup. If it
is not convenient to use these high-value resistors, an
equivalent “T” network, as shown in Figure 4, may be
substituted in place of the 3.9M . A 0.001 F to 0.01 F
capacitor should be connected from Gain Adjust (pin 34) to
CC
), negative supply (–V
Internal Reference and Op Amp.
resistors (20% carbon or better) should be
CC
), or logic supply (V
DD
) about