DAC1408D NXP [NXP Semiconductors], DAC1408D Datasheet - Page 2

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DAC1408D

Manufacturer Part Number
DAC1408D
Description
JESD204A-compliant D/A conversion for wideband communication & instrumentation
Manufacturer
NXP [NXP Semiconductors]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DAC1408D650HN/C1:5
Manufacturer:
Maxim
Quantity:
150
rate (up to 4.0 Gbps versus the standard rate of 3.125 Gbps,
a 28% increase) and transmitter reach (up to 100 cm versus
the standard reach of 20 cm, a 400% increase). The enhanced
CGV features include Multi Device Synchronization (MDS),
which is not specified, but informatively discussed in the
JEDEC specification. NXP has implemented this optional
feature to enable LTE MIMO base station and other advanced
multichannel applications. NXP’s implementation of MDS
enables up to sixteen DACs data streams to be sample
synchronized and phase coherent.
This new interface has numerous advantages over the traditional
parallel one: easy PCB layout, lower pin count, reduced PCB
layers and cost, lower radiated noise, selfsynchronous link, skew
compensation.
DAC1408D750 block diagram
DAC1408D series
www.nxp.com
© 2010 NXP B.V.
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The
information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and
may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof
does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Type
DAC1408D series
Related demoboard
DAC1408D650W0/DB
DAC1408D650W1/DB
DAC1408D750W0/DB
DAC1408D750W1/DB
DAC1408D650 demo board
DAC1408D650 demo board with Virtex 5 FPGA
DAC1408D750 demo board
DAC1408D750 demo board with Virtex 5 FPGA
Other features include a two’s complement or binary-offset data
format, and 74 dBc IMD3 at F
DAC1408D series also include an LVDS compatible clock with
multiplier capable of x2, x4 and x8 operation and internal
regulation to adjust the output full scale current up to 20 mA.
A digital offset correction can be used to adjust the common
mode level at the DAC output. And 2 embedded auxiliary DACs
-current mode sources allow offset compensation between the
DAC and the next stage in your transmission path.
Date of release: June 2010
Document order number : 9397 750 16888
Printed in the Netherlands
Description
DAC
Example of reference design
with DAC1408D750 and FPGA
DAC1408D750 demonstration
board, for easy connection to
Altera, Xilinx or Lattice
evaluation kit
= 640 Msps and F
www.nxp.com/dataconverters
OUT
= 154 MHz.

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