EPM3256A ALTERA [Altera Corporation], EPM3256A Datasheet - Page 26

• Manufacturer Part Number: EPM3256A
• Description: Programmable Logic Device Family
• Manufacturer: ALTERA [Altera Corporation]

MAX 3000A Programmable Logic Device Family Data Sheet
26
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
f
t
f
Symbol
CLR
PIA
LPA
Symbol
PD1
PD2
SU
H
CO1
CH
CL
ASU
AH
ACO1
ACH
ACL
CPPW
CNT
CNT
ACNT
ACNT
Table 14. EPM3032A Internal Timing Parameters (Part 2 of 2)
Table 15. EPM3064A External Timing Parameters
Register clear time
PIA delay
Low–power adder
Input to non–registered
output
I/O input to non–registered
output
Global clock setup time
Global clock hold time
Global clock to output delay C1 = 35 pF
Global clock high time
Global clock low time
Array clock setup time
Array clock hold time
Array clock to output delay
Array clock high time
Array clock low time
Minimum pulse width for
clear and preset
Minimum global clock
period
Maximum internal global
clock frequency
Minimum array clock period
Maximum internal array
clock frequency
Parameter
Parameter
(2)
(5)
C1 = 35 pF
C1 = 35 pF
(2)
(2)
(2)
(2)
C1 = 35 pF
(3)
(2)
(2),
(2)
(2),
Conditions
Conditions
(4)
(4)
(2)
(2)
(2)
Note (1)
222.2
222.2
Min
Min
2.8
0.0
1.0
2.0
2.0
1.6
0.3
1.0
2.0
2.0
2.0
–4
–4
Max
Max
4.5
4.5
3.1
4.3
4.5
4.5
1.2
0.9
2.5
Note (1)
135.1
135.1
Speed Grade
Speed Grade
Min
Min
4.7
0.0
1.0
3.0
3.0
2.6
0.4
1.0
3.0
3.0
3.0
–7
–7
Max
Max
1.9
1.5
4.0
7.5
7.5
5.1
7.2
7.4
7.4
100.0
100.0
Min
Min
6.2
0.0
1.0
4.0
4.0
3.6
0.6
1.0
4.0
4.0
4.0
Altera Corporation
–10
–10
Max
Max
10.0
10.0
10.0
10.0
2.6
2.1
5.0
7.0
9.6
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns