XCR3384XL-7FG324I XILINX [Xilinx, Inc], XCR3384XL-7FG324I Datasheet

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XCR3384XL-7FG324I

Manufacturer Part Number
XCR3384XL-7FG324I
Description
384 Macrocell CPLD
Manufacturer
XILINX [Xilinx, Inc]
Datasheet
DS024 (v1.3) August 10, 2001
Features
Table 1: Typical I
DS024 (v1.3) August 10, 2001
Advance Product Specification
Frequency (MHz)
Typical I
Lowest power 384 macrocell CPLD
7.5 ns pin-to-pin logic delays
System frequencies up to 127 MHz
384 macrocells with 9,600 usable gates
Available in small footprint packages
-
-
-
-
Optimized for 3.3V systems
-
-
-
-
Advanced system features
-
-
-
-
-
-
-
-
Fast ISP programming times
Port Enable pin for additional I/O
2.7V to 3.6V supply voltage at industrial grade voltage
range
Programmable slew rate control per output
Security bit prevents unauthorized access
Refer to XPLA3 family data sheet (DS012) for
architecture description
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
144-pin TQFP (118 user I/O)
208-pin PQFP (172 user I/O)
256-ball FBGA (212 user I/O)
324-ball FBGA (220 user I/O)
Ultra low power operation
5V tolerant I/O pins with 3.3V core supply
Advanced 0.35 micron five layer metal EEPROM
process
FZP™ CMOS design technology
In-system programming
Input registers
Predictable timing model
Up to 23 clocks available per function block
Excellent pin retention during design changes
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Four global clocks
Eight product term control terms per function block
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
CC
(mA)
CC
vs. Frequency at V
TBD
0
R
TBD
1
CC
TBD
10
= 3.3V, 25 C
TBD
0
0
20
www.xilinx.com
1-800-255-7778
14
TBD
40
XCR3384XL: 384 Macrocell CPLD
Advance Product Specification
Description
The XCR3384XL is a 3.3V, 384 macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic solutions. A total of 24 function blocks provide
9,600 usable gates. Pin-to-pin propagation delays are
7.5 ns with a maximum system frequency of 127 MHz.
TotalCMOS™ Design Technique for
Fast Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
performance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1
XCR3384XL TotalCMOS CPLD (data taken with 24
up/down, loadable 16-bit counters at 3.3V, 25°C).
Figure 1: XCR3384XL Typical I
140
120
100
80
60
40
20
0
TBD
60
and
0
Table 1
20
TBD
80
40
V
showing the I
CC
Frequency (MHz)
TBD
= 3.3V, 25 C
100
60
80
TBD
120
CC
CC
100
vs. Frequency of our
vs. Frequency at
TBD
120 140
140
DS024_01_112700
160
1

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XCR3384XL-7FG324I Summary of contents

Page 1

... Advance Product Specification 0 14 Description The XCR3384XL is a 3.3V, 384 macrocell CPLD targeted at power sensitive designs that require leading edge program- mable logic solutions. A total of 24 function blocks provide 9,600 usable gates. Pin-to-pin propagation delays are 7.5 ns with a maximum system frequency of 127 MHz. ...

Page 2

... XCR3384XL: 384 Macrocell CPLD DC Electrical Characteristics Over Recommended Operating Conditions Symbol Parameter (2) V Output High voltage OH V Output Low voltage OL I Input leakage current IL I I/O High-Z leakage current IH I Standby current CCSB (4,5) I Dynamic current CC (6) C Input pin capacitance IN C Clock input capacitance ...

Page 3

... These parameters guaranteed by design and/or characterization, not testing. 5. Typical current draw during configuration 3.6V. 6. Output pF. L DS024 (v1.3) August 10, 2001 Advance Product Specification -7 Min. Max. - 7.0 (3) - 7.5 - 4.5 2 3 127 - TBD - TBD - 9.0 (6) - 9.0 - 8.0 - 9.0 www.xilinx.com 1-800-255-7778 XCR3384XL: 384 Macrocell CPLD (1,2) -10 -12 Min. Max. Min. Max. - 9.0 - 10.8 - 10.0 - 12.0 - 5.8 - 6.9 3.0 - 3.0 - 6 4.0 - 5.0 - 6 102 ...

Page 4

... XCR3384XL: 384 Macrocell CPLD Internal Timing Parameters Symbol Parameter Buffer Delays T Input buffer delay IN T Fast input buffer delay FIN T Global clock buffer delay GCK T Output buffer delay OUT T Output buffer enable/disable delay EN Internal Register and Combinatorial Delays T Latch transparent delay ...

Page 5

... Note: For T POD Figure 3: AC Load Circuit +3.0V 0V Measurements All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. DS024_04_11800 PD2 www.xilinx.com 1-800-255-7778 XCR3384XL: 384 Macrocell CPLD Values 390 390 Open Closed Closed Open Closed Closed , ...

Page 6

... Table 3: XCR3384XL I/O Pins (Continued) Function Block 3 FT256 FG324 3 212 220 FT256 FG324 3 E15 G22 3 F13 H20 3 E16 H21 3 F14 J19 3 F15 J21 ...

Page 7

... R Table 3: XCR3384XL I/O Pins (Continued) Function Macro- Block cell TQ144 PQ208 ...

Page 8

... Table 3: XCR3384XL I/O Pins (Continued) Function Macro- FT256 FG324 Block A13 A18 13 D12 C17 13 B13 B17 C12 A17 14 A12 D16 14 D11 C16 14 A11 ...

Page 9

... R Table 3: XCR3384XL I/O Pins (Continued) Function Macro- Block cell TQ144 PQ208 147 148 149 150 151 ...

Page 10

... Table 3: XCR3384XL I/O Pins (Continued) Function FT256 FG324 Block - - AA4 24 - AB3 AA3 (1) (1) ( ...

Page 11

... R Table 4: XCR3384XL Global, JTAG, Port Enable, Power, and No Connect Pins Pin Type TQ144 IN0 / CLK0 128 IN1 / CLK1 127 IN2 / CLK2 126 IN3 / CLK3 125 TCK 86 TDI 131 TDO 121 TMS 22 PORT_EN 33 V 24, 50, 51, 58, 73, 76, 95, CC 115, 123, 130, 144 ...

Page 12

... Update TSUF spec to meet UMC characterization data. Added Typical I/V curve, added package. 04/19/01 1.2 Updated Typical I/V curve, 08/10/01 1.3 Updated AC Electrical Characterisitics; Internal Timing Parameters; added TQ144 package and pinouts. 12 XCR3384XL -7 PQ 208 C Package 256-ball Fineline BGA Package 208 Plastic PQFP Plastic FBGA PQ208 Revision Table 2: Total User I/O ...

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