XC9536XL-4CS48I XILINX [Xilinx, Inc], XC9536XL-4CS48I Datasheet

XC9536XL-4CS48I

Manufacturer Part Number

XC9536XL-4CS48I

Description

XC9536XL High PerformanceCPLD

Manufacturer

XILINX [Xilinx, Inc]

Datasheet

1.XC9536XL-4CS48I.pdf (7 pages)

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DS058 (v1.2) June 25, 2001

Features

•

Description

The XC9536XL is a 3.3V CPLD targeted for high-perfor

mance, low-voltage applications in leading-edge communi

DS058 (v1.2) June 25, 2001

Preliminary Product Specification

5 ns pin-to-pin logic delays

System frequency up to 178 MHz

36 macrocells with 800 usable gates

Available in small footprint packages

Optimized for high-performance 3.3V systems

Advanced system features

Fast concurrent programming

Slew rate control on individual outputs

Enhanced data security features

Excellent quality and reliability

Pin-compatible with 5V-core XC9536 device in the

44-pin PLCC package and the 48-pin CSP package

44-pin PLCC (34 user I/O pins)

44-pin VQFP (34 user I/O pins)

48-pin CSP (36 user I/O pins)

64-pin VQFP (36 user I/O pins)

Low power operation

5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V

signals

3.3V or 2.5V output capability

Advanced 0.35 micron feature size CMOS

FastFLASH™ technology

In-system programmable

Superior pin-locking and routability with

FastCONNECT II™ switch matrix

Extra wide 54-input Function Blocks

Up to 90 product-terms per macrocell with

individual product-term allocation

Local clock inversion with three global and one

product-term clocks

Individual output enable per output pin

Input hysteresis on all user and boundary-scan pin

inputs

Bus-hold circuitry on all user pin inputs

Full IEEE Standard 1149.1 boundary-scan (JTAG)

Endurance exceeding 10,000 program/erase

cycles

20 year data retention

ESD protection exceeding 2,000V

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

www.xilinx.com

1-800-255-7778

XC9536XL High Performance

CPLD

Preliminary Product Specification

cations and computing systems. It is comprised of two

54V18 Function Blocks, providing 800 usable gates with

propagation delays of 5 ns. See

overview.

Power Estimation

Power dissipation in CPLDs can vary substantially depend

ing on the system frequency, design application and output

loading. To help reduce power dissipation, each macrocell

in a XC9500XL device may be configured for low-power

mode (from the default high-performance mode). In addi

tion, unused product-terms and macrocells are automati

cally deactivated by the software to further conserve power.

For a general estimate of I

used:

Where:

This calculation is based on typical operating conditions

using a pattern of 16-bit up/down counters in each Function

Block with no output loading. The actual I

with the design application and should be verified during

normal system operation.

Figure 1

Figure 1: Typical I

(mA) = MC

MC = Total number of macrocells used

f = Clock frequency (MHz)

shows the above estimation in a graphical form.

= Macrocells in low-power mode

= Macrocells in high-performance (default) mode

(0.5) + MC

Clock Frequency (MHz)

vs. Frequency for XC9536XL

100

, the following equation may be

125 MHz

(0.3) + MC(0.0045 mA/MHz) f

Figure 2

150

178 MHz

for architecture

200

DS058_01_061101

value varies

250

Related parts for XC9536XL-4CS48I

XC9536XL-4CS48I Summary of contents

Page 1

... PLCC package and the 48-pin CSP package Description The XC9536XL is a 3.3V CPLD targeted for high-perfor mance, low-voltage applications in leading-edge communi © 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. ...

Page 2

... I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR 2 I/O/GTS Function Block outputs (indicated by the bold line) drive the I/O Blocks directly. 2 JTAG In-System Programming Controller Controller I/O Blocks Figure 2: XC9536XL Architecture www.xilinx.com 1-800-255-7778 54 Function 18 Block 1 Macrocells Function 18 Block 2 Macrocells DS058_02_081500 DS058 (v1.2) June 25, 2001 Preliminary Product Specification ...

Page 3

... 500 Max GND Max GND GND 1.0 MHz V = GND, No load 1.0 MHz www.xilinx.com 1-800-255-7778 XC9536XL High Performance CPLD Value –0.5 to 4.0 –0.5 to 5.5 –0.5 to 5.5 –65 to +150 +260 +150 Min Max 3.0 3 +85 C 3.0 3.6 3.0 3.6 2.3 2.7 0 0.80 2 ...

Page 4

... XC9536XL High Performance CPLD AC Characteristics Symbol Parameter T I/O to output valid PD T I/O setup time before GCK SU T I/O hold time after GCK H T GCK to output valid CO f Multiple FB internal operating frequency SYSTEM T I/O setup time before p-term clock input PSU T I/O hold time after p-term clock input ...

Page 5

... Internal logic delay LOGI T Internal low power logic delay LOGILP Feedback Delays T FastCONNECT II feedback delay F Time Adders T Incremental product term allocator delay PTA T Slew-rate limited delay SLEW DS058 (v1.2) June 25, 2001 Preliminary Product Specification XC9536XL High Performance CPLD XC9536XL-5 XC9536XL-7 Min Max Min Max - 1.5 - 2.3 - 1.1 - 1 ...

Page 6

... Notes: 1. Global control pin. XC9536XL Global, JTAG and Power Pins Pin Type PC44 I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GSR TCK TDI TDO TMS V 3.3V 21, 41 CCINT V 2.5V/3.3V CCIO GND 10, 23 Connects 6 BScan ...

Page 7

... Removed -4 device. Added C4 and D4 pins to CS48 No Connects in pinout table. Added industrial availability to -7 device. DS058 (v1.2) June 25, 2001 Preliminary Product Specification XC9536XL - ackage 44-pin Plastic Lead Chip Carrier (PLCC) 44-pin Quad Flat Pack (VQFP) 48-pin Chip Scale Package 64-pin Quad Flat Pack (VQFP) ...

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