XCR3512XL-10FG324C XILINX [Xilinx, Inc], XCR3512XL-10FG324C Datasheet
XCR3512XL-10FG324C
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XCR3512XL-10FG324C Summary of contents
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... Advance Product Specification 0 14 Description The XCR3512XL is a 3.3V, 512 macrocell CPLD targeted at power sensitive designs that require leading edge program- mable logic solutions. A total of 32 function blocks provide 12,800 usable gates. Pin-to-pin propagation delays are 7.5 ns with a maximum system frequency of 127 MHz. ...
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... XCR3512XL: 512 Macrocell CPLD DC Electrical Characteristics Over Recommended Operating Conditions Symbol Parameter (2) V Output High voltage OH V Output Low voltage OL I Input leakage current IL I I/O High-Z leakage current IH I Standby current CCSB (4,5) I Dynamic current CC (6) C Input pin capacitance IN C Clock input capacitance ...
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... Typical current draw during configuration 3.6V. 6. Output pF. L DS081 (v1.2) September 4, 2001 Advance Product Specification I (3.3V (2.7V) OH 0.5 1 1.5 2 2.5 Volts Figure 2: Typical I/V Curve for the XPLA3 Family -7 Min. (3) (6) www.xilinx.com 1-800-255-7778 XCR3512XL: 512 Macrocell CPLD I (3.3V 3.5 4 4.5 5 DS012_10_041901 -10 -12 Max. Min. Max. Min 5 ...
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... XCR3512XL: 512 Macrocell CPLD Internal Timing Parameters Symbol Parameter Buffer Delays T Input buffer delay IN T Fast input buffer delay FIN T Global clock buffer delay GCK T Output buffer delay OUT T Output buffer enable/disable delay EN Internal Register and Combinatorial Delays T Latch transparent delay ...
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... Note: For T POD Figure 3: AC Load Circuit +3.0V 0V Measurements All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. DS024_04_11800 PD2 www.xilinx.com 1-800-255-7778 XCR3512XL: 512 Macrocell CPLD Values 390 390 Open Closed Closed Open Closed Closed , ...
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... Table 3: XCR3512XL I/O Pins (Continued) Function Block FT256 FG324 2 212 260 FT256 FG324 3 C14 C21 3 D13 C20 3 - B22 3 A15 B21 ...
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... R Table 3: XCR3512XL I/O Pins (Continued) Function Block Macrocell PQ208 5 1 197 196 195 194 5 16 193 ...
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... Table 3: XCR3512XL I/O Pins (Continued) Function FT256 FG324 Block - - M13 Y21 11 P15 W20 12 L12 W21 12 N16 Y22 12 N13 AB21 12 R15 Y19 12 M12 ...
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... R Table 3: XCR3512XL I/O Pins (Continued) Function Block Macrocell PQ208 ( ...
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... Table 3: XCR3512XL I/O Pins (Continued) Function FT256 FG324 Block ...
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... R Table 3: XCR3512XL I/O Pins (Continued) Function Block Macrocell PQ208 139 138 23 1 173 175 ( 176 23 15 177 23 16 178 24 1 137 ...
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... Table 3: XCR3512XL I/O Pins (Continued) Function FT256 FG324 Block R3 AA4 ...
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... Notes: 1. JTAG pins. DS081 (v1.2) September 4, 2001 Advance Product Specification Table 4: XCR3512XL Global, JTAG, Port Enable, Power, and No Connect Pins FT256 FG324 Pin Type - - IN0 / CLK0 IN1 / CLK1 - - IN2 / CLK2 - - IN3 / CLK3 - - TCK - - TDI - - TDO ...
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... The following table shows the revision history for this document Date Version 04/11/01 1.0 Initial Xilinx release. 04/19/01 1.1 Updated Typical I/V curve, 09/04/01 1.2 Updated AC Electrical: added T temperature. 14 XCR3512XL -10 PQ 208 C Package 256-ball Fineline BGA Package 256 324 Plastic FBGA Plastic FBGA FT256 FG324 ...