XC9536XV-7PC44I XILINX [Xilinx, Inc], XC9536XV-7PC44I Datasheet

XC9536XV-7PC44I

Manufacturer Part Number

XC9536XV-7PC44I

Description

High-performance CPLD

Manufacturer

XILINX [Xilinx, Inc]

Datasheet

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DS053 (v2.6) April 15, 2005

Features

•

Description

The XC9536XV is a 2.5V CPLD targeted for high-perfor-

mance, low-voltage applications in leading-edge communi-

cations and computing systems. It is comprised of two

54V18 Function Blocks, providing 800 usable gates with

propagation delays of 5 ns. See

overview.

Power Estimation

Power dissipation in CPLDs can vary substantially depend-

ing on the system frequency, design application and output

loading. To help reduce power dissipation, each macrocell

in a XC9500XV device may be configured for low-power

mode (from the default high-performance mode). In addi-

tion, unused product-terms and macrocells are automati-

cally deactivated by the software to further conserve power.

DS053 (v2.6) April 15, 2005

Product Specification

36 macrocells with 800 usable gates

Available in small footprint packages

Optimized for high-performance 2.5V systems

Advanced system features

Fast concurrent programming

Slew rate control on individual outputs

Enhanced data security features

Excellent quality and reliability

Pin-compatible with 3.3V-core XC9536XL device in the

44-pin PLCC, 44-pin VQFP, and 48-pin CSP packages

44-pin PLCC (34 user I/O pins)

44-pin VQFP (34 user I/O pins)

48-pin CSP (36 user I/O pins)

Low power operation

Multi-voltage operation

In-system programmable

Superior pin-locking and routability with

Fast CONNECT™ II switch matrix

Extra wide 54-input Function Blocks

Up to 90 product-terms per macrocell with

individual product-term allocation

Local clock inversion with three global and one

product-term clocks

Individual output enable per output pin

Input hysteresis on all user and boundary-scan pin

inputs

Bus-hold circuitry on all user pin inputs

Full IEEE Standard 1149.1 boundary-scan (JTAG)

20 year data retention

ESD protection exceeding 2,000V

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

Figure 2

for architecture

www.xilinx.com

XC9536XV High-performance

CPLD

Product Specification

For a general estimate of I

used:

Separating internal and I/O power here is convenient

because XC9500XV CPLDs also separate the correspond-

ing power pins. P

tance driven, so it is handled by I = CVf. I

situation that reflects the actual design considered and the

internal switching speeds. An estimation expression for

where:

This calculation was derived from laboratory measurements

of an XC9500XV part filled with 16-bit counters and allowing

a single output (the LSB) to be enabled. The actual I

value varies with the design application and should be veri-

fied during normal system operation.

above estimation in a graphical form. For a more detailed

discussion of power consumption in this device, see Xilinx

application note

XC9500XV Designs.”

CCINT

Figure 1: Typical I

frequently a good estimate

MAX

+ 0.171) + 0.04(MC

(mA) = MC

(taken from simulation) is:

TOG

TOTAL

= max clocking frequency in the device

= average p-terms used over low power macrocell

= average p-terms used per high speed macrocell

= #macrocells used in low power mode

= # macrocells used in high speed mode

= % macrocells toggling on each clock (12% is

= P

XAPP361, “Planning for High Speed

INT

(0.122 X PT

is a strong function of the load capaci-

+ P

Clock Frequency (MHz)

vs. Frequency for XC9536XV

= I

, the following equation may be

+ MC

CCINT

100

+ 0.238) + MC

120 MHz

) x f

x V

Figure 1

MAX

150

CCINT

DS053_01_121501

CCINT

200 MHz

x MC

+ P

shows the

is another

200

TOG

(0.042 x

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XC9536XV-7PC44I Summary of contents

Page 1

... Pin-compatible with 3.3V-core XC9536XL device in the 44-pin PLCC, 44-pin VQFP, and 48-pin CSP packages Description The XC9536XV is a 2.5V CPLD targeted for high-perfor- mance, low-voltage applications in leading-edge communi- cations and computing systems comprised of two 54V18 Function Blocks, providing 800 usable gates with propagation delays ...

Page 2

... Function block outputs (indicated by the bold line) drive the I/O Blocks directly. Supported I/O Standards Table 1: IOSTANDARD Options IOSTANDARD V CCIO LVTTL 3.3V LVCMOS2 2.5V X25TO18 1.8V The XC9536XV CPLD features both LVCMOS and LVTTL I/O implementations. See Table 1 for I/O standard voltages JTAG In-System Programming Controller 1 Controller I/O Blocks ...

Page 3

... Program/Erase Cycles (Endurance Electrostatic Discharge (ESD) ESD DS053 (v2.6) April 15, 2005 Product Specification Description (1) (1) Packaging. Parameter Commercial Industrial T = –40 A Parameter www.xilinx.com XC9536XV High-performance CPLD Value –0.5 to 2.7 –0.5 to 3.6 –0.5 to 3.6 –0.5 to 3.6 –65 to +150 +150 Min Max +70 C 2. ...

Page 4

... XC9536XV High-performance CPLD DC Characteristics (Over Recommended Operating Conditions) Symbol Parameter V Output high voltage for 3.3V outputs OH Output high voltage for 2.5V outputs Output high voltage for 1.8V outputs V Output low voltage for 3.3V outputs OL Output low voltage for 2.5V outputs Output low voltage for 1.8V outputs I Input leakage current ...

Page 5

... T Adjacent macrocell p-term allocator delay PTA2 T Slew-rate limited delay SLEW DS053 (v2.6) April 15, 2005 Product Specification Output Type V CCIO 3.3V 2. 1.8V Figure 3: AC Load Circuit Parameter www.xilinx.com XC9536XV High-performance CPLD TEST 1 2 3.3V 320 360 2.5V 250 660 1.8V 10K 14K XC9536XV-5 XC9536XV-7 Min Max ...

Page 6

... Notes: 1. Global control pin. XC9536XV Global, JTAG and Power Pins Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GSR TCK TDI TDO TMS V 2.5V CCINT V 1.8vV/2.5V/3.3V CCIO GND No Connects 6 BScan Function CS48 Order ...

Page 7

... Device Ordering and (pin-to-pin Part Marking Number delay) XC9536XV-5PC44C 5 ns XC9536XV-5VQ44C 5 ns XC9536XV-5CS48C 5 ns XC9536XV-7PC44C 7.5 ns XC9536XV-7VQ44C 7.5 ns XC9536XV-7CS48C 7.5 ns XC9536XV-7PC44I 7.5 ns XC9536XV-7VQ44I 7.5 ns XC9536XV-7CS48I 7.5 ns Notes Commercial 0° to +70° Industrial Some packages available in Pb-free option. See DS053 (v2.6) April 15, 2005 Product Specification R ...

Page 8

... XC9536XV High-performance CPLD Revision History Date Revision No. 02/01/00 1.1 Initial Xilinx release. Advance information specification. 01/29/01 2.0 Added -3 performance specification and VQ44 package. Deleted VQ64 package. Updated I 05/15/01 2.1 Updated I Characteristics and Internal Timing Parameters 08/27/01 2.2 Changed V - added "low" current 05/31/02 2.3 Updated I C4 and D4 as NCs in the CS48 package pinouts. Added second test condition and max measurement to I Information ...

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