XC9572-7TQ100I XILINX [Xilinx, Inc], XC9572-7TQ100I Datasheet

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XC9572-7TQ100I

Manufacturer Part Number
XC9572-7TQ100I
Description
XC9572 In-System Programmable CPLD
Manufacturer
XILINX [Xilinx, Inc]
Datasheet

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Part Number:
XC9572-7TQ100I
Manufacturer:
XILINX
0
December 4, 1998 (Version 3.0)
Features
• 7.5 ns pin-to-pin logic delays on all pins
• f
• 72 macrocells with 1,600 usable gates
• Up to 72 user I/O pins
• 5 V in-system programmable (ISP)
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
• Programmable power reduction mode in each
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs
• 3.3 V or 5 V I/O capability
• Advanced CMOS 5V FastFLASH technology
• Supports parallel programming of more than one
• Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP
Description
The XC9572 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of four
36V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 7.5 ns. See
ture overview.
December 4, 1998 (Version 3.0)
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
- 90 product terms drive any or all of 18 macrocells
- Global and product term clocks, output enables, set
support
macrocell
XC9500 concurrently
and 100-pin TQFP packages
CNT
temperature range
within Function Block
and reset signals
to 125 MHz
Figure 2
for the architec-
1
1
1*
XC9572 In-System Programmable
CPLD
Product Specification
Power Management
Power dissipation can be reduced in the XC9572 by config-
uring macrocells to standard or low-power modes of opera-
tion. Unused macrocells are turned off to minimize power
dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
I
MC
Where:
MC
MC
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1
CC
Figure 1: Typical I
HP
HP
LP
(mA) =
= Macrocells in low-power mode
(125)
(1.7) + MC
= Macrocells in high-performance mode
200
(65)
100
shows a typical calculation for the XC9572 device.
0
LP
(0.9) + MC (0.006 mA/MHz) f
CC
Clock Frequency (MHz)
vs. Frequency for XC9572
50
100
(160)
(100)
1

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XC9572-7TQ100I Summary of contents

Page 1

... CPLD Product Specification 1 1* Power Management Power dissipation can be reduced in the XC9572 by config- uring macrocells to standard or low-power modes of opera- tion. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specific operating conditions using the following equation: ...

Page 2

... XC9572 In-System Programmable CPLD 1 JTAG Port I/O I/O I/O I/O I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR 2 I/O/GTS Figure 2: XC9572 Architecture Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly 2 3 JTAG Controller I/O Blocks In-System Programming Controller 36 Function 18 Block 1 Macrocells Function 18 Block 2 Macrocells ...

Page 3

... IL V High-level input voltage IH V Output voltage O Note: 1. Numbers in parenthesis are for industrial temperature range versions. Endurance Characteristics Symbol Parameter Data Retention t DR Program/Erase Cycles N PE December 4, 1998 (Version 3.0) XC9572 In-System Programmable CPLD Parameter 1 Min 4.75 (4.5) 4.75 (4.5) 3.0 0 2.0 0 Min 20 10,000 Value Units -0.5 to 7 ...

Page 4

... XC9572 In-System Programmable CPLD DC Characteristics Over Recommended Operating Conditions Symbol V Output high voltage for 5 V operation OH Output high voltage for 3.3 V operation V Output low voltage for 5 V operation OL Output low voltage for 3.3 V operation I Input leakage current IL I I/O high-Z leakage current IH C I/O capacitance ...

Page 5

... Time Adders t 3 Incremental Product Term Allocator delay PTA t Slew-rate limited delay SLEW Note multiplied by the span of the function as defined in the family data sheet. PTA December 4, 1998 (Version 3.0) XC9572 In-System Programmable CPLD XC9572-7 XC9572-10 XC9572-15 Min Max Min Max Min Max 2.5 3.5 1.5 2 ...

Page 6

... XC9572 In-System Programmable CPLD XC9572 I/O Pins Function Macrocell Block 44 84 100 1 1 – – – – – ...

Page 7

... XC9572 Global, JTAG and Power Pins Pin Type PC44 I/O/GCK1 5 I/O/GCK2 6 I/O/GCK3 7 I/O/GTS1 42 I/O/GTS2 40 I/O/GSR 39 TCK 17 TDI 15 TDO 30 TMS 21,41 CCINT V 3.3 V CCIO GND 10,23,31 No Connects – December 4, 1998 (Version 3.0) XC9572 In-System Programmable CPLD PC84 PQ100 ...

Page 8

... C(I) – Commercial = Industrial = –40 to +85 C Revision Control Date 12/04/98 Update AC Characteristics and Internal Parameters 8 XC9572 -7 PQ 100 C Packaging Options PC44 PC84 PQ100 100-Pin Plastic Quad Flat Pack (PQFP) TQ100 100-Pin Very Thin Quad Flat Pack (TQFP) Temperature Options ...

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