EPF81188A ALTERA [Altera Corporation], EPF81188A Datasheet
EPF81188A
Available stocks
Related parts for EPF81188A
EPF81188A Summary of contents
Page 1
... Yes No Yes FLEX 8000 Programmable Logic Device Family Table 1) EPF8820A EPF81188A EPF81500A 8,000 12,000 820 1,188 84 126 672 1,008 152 184 Yes No Data Sheet 16,000 1,500 162 1,296 208 Yes 1 ...
Page 2
... EPF8452A 68 68 EPF8636A 68 EPF8820A EPF81188A EPF81500A Note: (1) FLEX 8000 device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), and pin-grid array (PGA) packages. ...
Page 3
Table 3. FLEX 8000 Performance Application 16-bit loadable counter 16-bit up/down counter 24-bit accumulator 16-bit address decode 16-to-1 multiplexer f Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet FLEX 8000 devices provide a large number of storage elements ...
Page 4
FLEX 8000 Programmable Logic Device Family Data Sheet f Functional Description 4 FLEX 8000 devices contain an optimized microprocessor interface that permits the microprocessor to configure FLEX 8000 devices serially, in parallel, synchronously, or asynchronously. The interface also enables the ...
Page 5
Figure 1. FLEX 8000 Device Block Diagram I/O Element (IOE) IOE IOE Logic Array Block (LAB) IOE IOE Logic Element (LE) Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 1 shows a block diagram of the FLEX ...
Page 6
FLEX 8000 Programmable Logic Device Family Data Sheet Figure 2. FLEX 8000 Logic Array Block LAB Local Interconnect (32 channels) LAB Control Signals 6 Logic Array Block A logic array block (LAB) consists of eight LEs, their associated carry and ...
Page 7
Figure 3. FLEX 8000 LE DATA1 DATA2 DATA3 DATA4 LABCTRL1 LABCTRL2 LABCTRL3 LABCTRL4 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Each LAB provides four control signals that can be used in all eight LEs. Two of these ...
Page 8
FLEX 8000 Programmable Logic Device Family Data Sheet 8 The FLEX 8000 architecture provides two dedicated high-speed data paths—carry chains and cascade chains—that connect adjacent LEs without using local interconnect paths. The carry chain supports high- speed counters and adders; ...
Page 9
Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 4. FLEX 8000 Carry Chain Operation Carry- Carry a2 LUT b2 Carry Chain a n LUT b n Carry Chain LUT Carry Chain Cascade Chain With ...
Page 10
FLEX 8000 Programmable Logic Device Family Data Sheet Figure 5. FLEX 8000 Cascade Chain Operation AND Cascade Chain d[3..0] LUT d[7..4] LUT d[(4 n- 1)..4( n- 1)] LUT 10 The MAX+PLUS II Compiler can create cascade chains automatically during design ...
Page 11
Figure 6. FLEX 8000 LE Operating Modes Normal Mode DATA1 DATA2 DATA3 DATA4 Arithmetic Mode DATA1 DATA2 Up/Down DATA1 (ena) DATA2 (nclr) DATA3 (data) DATA4 (nload) Clearable Counter Mode DATA1 (ena) DATA2 (nclr) DATA3 (data) DATA4 (nload) Altera Corporation FLEX ...
Page 12
FLEX 8000 Programmable Logic Device Family Data Sheet 12 Normal Mode The normal mode is suitable for general logic applications and wide decoding functions that can take advantage of a cascade chain. In normal mode, four data inputs from the ...
Page 13
Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Internal Tri-State Emulation Internal tri-state emulation provides internal tri-stating without the limitations of a physical tri-state bus physical tri-state bus, the tri-state buffers’ output enable signals select the ...
Page 14
FLEX 8000 Programmable Logic Device Family Data Sheet Figure 7. FLEX 8000 LE Asynchronous Clear & Preset Modes Asynchronous Clear VCC PRN D Q CLRN LABCTRL1 or LABCTRL2 Asynchronous Load with Clear NOT LABCTRL1 (Asynchronous Load) DATA3 (Data) NOT LABCTRL2 ...
Page 15
Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Asynchronous Clear A register is cleared by one of the two LABCTRL signals. When the CLRn port receives a low signal, the register is set to zero. Asynchronous Preset An ...
Page 16
FLEX 8000 Programmable Logic Device Family Data Sheet 16 FastTrack Interconnect In the FLEX 8000 architecture, connections between LEs and device I/O pins are provided by the FastTrack Interconnect, a series of continuous horizontal (row) and vertical (column) routing channels ...
Page 17
... Table 4. FLEX 8000 FastTrack Interconnect Resources Device Rows Channels per Row EPF8282A 2 EPF8282AV EPF8452A 2 EPF8636A 3 EPF8820A 4 EPF81188A 6 EPF81500A 6 Figure 9 shows the interconnection of four adjacent LABs, with row, column, and local interconnects, as well as the associated cascade and carry chains. Columns Channels per Column 168 13 168 ...
Page 18
FLEX 8000 Programmable Logic Device Family Data Sheet Figure 9. FLEX 8000 Device Interconnect Resources Each LAB is named according to its physical row ( etc.) and column ( etc.) position within the device. Column Interconnect ...
Page 19
... When an IOE is used as an output, the signal is driven by an n-to-1 multiplexer that selects the row channels. The size of the multiplexer varies with the number of columns in a device. EPF81500A devices use a 27-to-1 multiplexer; EPF81188A, EPF8820A, EPF8636A, and EPF8452A devices use a 21-to-1 multiplexer; and EPF8282A and EPF8282AV devices use a 13-to-1 multiplexer. Eight IOEs are connected to each side of the row channels ...
Page 20
... Numbers in parentheses are for EPF81500A devices. See Each IOE can drive up to two row channels. Row Interconnect Each IOE is driven by an n-to-1 multiplexer. Note for EPF8282A and EPF8282AV devices. ( for EPF8452A, EPF8636A, EPF8820A, and EPF81188A devices for EPF81500A devices. 20 Note (1 168 (216) 168 ...
Page 21
Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 12. FLEX 8000 Column-to-IOE Connections Each IOE is driven by an IOE 8-to-1 multiplexer. 8 Column Interconnect In addition to general-purpose I/O pins, FLEX 8000 devices have four dedicated ...
Page 22
... Figure 13. FLEX 8000 Peripheral Bus Numbers in parentheses are for EPF81500A devices. Dedicated Inputs 1 2 Row Channels n Note (1) Note for EPF8282A and EPF8282AV devices. ( for EPF8452A, EPF8636A, EPF8820A, and EPF81188A devices for EPF81500A devices. Programmable Inversion 4 Altera Corporation Peripheral Control Signals ...
Page 23
... Designers can specify the slew rate on a pin-by-pin basis during design entry or assign a default slew rate to all pins on a global basis. For more information on high-speed system design Note 75 (High-Speed Board Designs) EPF8820A EPF81188A Row A Row E Row C Row B Row B ...
Page 24
... MultiVolt I/O Interface The FLEX 8000 device architecture supports the MultiVolt I/O interface feature, which allows EPF81500A, EPF81188A, EPF8820A, and EPF8636A devices to interface with systems with differing supply voltages. These devices in all packages—except for EPF8636A devices in 84-pin PLCC packages—can be set for 3.3-V or 5.0-V I/O pin operation. These devices ...
Page 25
Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 14. EPF8282A, EPF8282AV, EPF8636A, EPF8820A & EPF81500A JTAG Waveforms TMS TDI t JCP t t JCH JCL TCK t JPZX TDO t JSSU Signal to Be Captured t JSZX ...
Page 26
FLEX 8000 Programmable Logic Device Family Data Sheet f Generic Testing 26 Table 7. JTAG Timing Parameters & Values Symbol Parameter t TCK clock period JCP t TCK clock high time JCH t TCK clock low time JCL t JTAG ...
Page 27
Operating Conditions FLEX 8000 5.0-V Device Absolute Maximum Ratings Symbol Parameter V Supply voltage input voltage output current, per pin OUT T Storage temperature STG T Ambient temperature AMB T Junction temperature J FLEX ...
Page 28
FLEX 8000 Programmable Logic Device Family Data Sheet FLEX 8000 5.0-V Device DC Operating Conditions Symbol Parameter V High-level input voltage IH V Low-level input voltage IL V 5.0-V high-level TTL output OH voltage 3.3-V high-level TTL output voltage 3.3-V ...
Page 29
Notes to tables: Operating Requirements for Altera Devices Data Sheet (1) See the (2) Minimum DC input is –0.3 V. During transitions, the inputs may undershoot to –2 overshoot to 7.0 V for periods shorter than 20 ns ...
Page 30
FLEX 8000 Programmable Logic Device Family Data Sheet FLEX 8000 3.3-V Device Capacitance Symbol Parameter C Input capacitance IN C Output capacitance OUT Notes to tables: Operating Requirements for Altera Devices Data Sheet (1) See the (2) Minimum DC input ...
Page 31
Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 17. Output Drive Characteristics of EPF8282A Devices with 5.0-V V 150 120 Figure 18 shows the typical output drive characteristics of EPF8282AV devices. Figure 18. ...
Page 32
FLEX 8000 Programmable Logic Device Family Data Sheet Timing Model Table 8. FLEX 8000 Internal Timing Parameters Symbol t IOE register data delay IOD t IOE register control signal delay IOC t Output enable delay IOE t IOE register clock-to-output ...
Page 33
Table 9. FLEX 8000 LE Timing Parameters Symbol t LUT delay for data-in LUT t LUT delay for carry-in CLUT t LUT delay for LE register feedback RLUT t Cascade gate delay GATE t Cascade chain routing delay CASC t ...
Page 34
FLEX 8000 Programmable Logic Device Family Data Sheet Notes to tables: (1) Internal timing parameters cannot be measured explicitly. They are worst-case delays based on testable and external parameters specified by Altera. Internal timing parameters should be used for estimating ...
Page 35
Figure 19. FLEX 8000 Timing Model Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet 35 ...
Page 36
FLEX 8000 Programmable Logic Device Family Data Sheet EPF8282A Internal Timing Parameters EPF8282A I/O Element Timing Parameters A-2 Speed Grade Symbol Min t IOD t IOC t IOE t IOCO t IOCOMB t 1.4 IOSU t 0.0 IOH t IOCLR ...
Page 37
EPF8282A LE Timing Parameters A-2 Speed Grade Symbol Min t LUT t CLUT t RLUT t GATE t CASC t CICO t CGEN t CGENR 4 4 COMB t 0.8 SU ...
Page 38
FLEX 8000 Programmable Logic Device Family Data Sheet 38 EPF8282AV Internal Timing Parameters EPF8282AV I/O Element Timing Parameters Symbol A-3 Speed Grade Min t IOD t IOC t IOE t IOCO t IOCOMB t 1.8 IOSU t 0.0 IOH t ...
Page 39
Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet EPF8282AV Logic Element Timing Parameters Symbol A-3 Speed Grade Min t LUT t CLUT t RLUT t GATE t CASC t CICO t CGEN t CGENR 4.0 ...
Page 40
FLEX 8000 Programmable Logic Device Family Data Sheet EPF8452A Internal Timing Parameters EPF8452A I/O Element Timing Parameters A-2 Speed Grade Symbol Min t IOD t IOC t IOE t IOCO t IOCOMB t 1.4 IOSU t 0.0 IOH t IOCLR ...
Page 41
EPF8452A LE Timing Parameters A-2 Speed Grade Symbol Min t LUT t CLUT t RLUT t GATE t CASC t CICO t CGEN t CGENR 4 4 COMB t 0.8 SU ...
Page 42
FLEX 8000 Programmable Logic Device Family Data Sheet EPF8636A Internal Timing Parameters EPF8636A I/O Element Timing Parameters Symbol Min t IOD t IOC t IOE t IOCO t IOCOMB t 1.4 IOSU t 0.0 IOH t IOCLR ...
Page 43
EPF8636A LE Timing Parameters Symbol t LUT t CLUT t RLUT t GATE t CASC t CICO t CGEN t CGENR COMB PRE t CLR EPF8636A ...
Page 44
FLEX 8000 Programmable Logic Device Family Data Sheet EPF8820A Internal Timing Parameters EPF8820A I/O Element Timing Parameters A-2 Speed Grade Symbol Min t IOD t IOC t IOE t IOCO t IOCOMB t 1.4 IOSU t 0.0 IOH t IOCLR ...
Page 45
EPF8820A LE Timing Parameters A-2 Speed Grade Symbol Min t LUT t CLUT t RLUT t GATE t CASC t CICO t CGEN t CGENR 4 4 COMB t 0.8 SU ...
Page 46
... FLEX 8000 Programmable Logic Device Family Data Sheet EPF81188A Internal Timing Parameters EPF81188A I/O Element Timing Parameters Symbol t IOD t IOC t IOE t IOCO t IOCOMB t IOSU t IOH t IOCLR OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 EPF81188A Interconnect Timing Parameters Symbol t LABCASC t LABCARRY t LOCAL ...
Page 47
... GATE t CASC t CICO t CGEN t CGENR 4 4 COMB PRE t CLR EPF81188A External Timing Parameters Symbol Min t DRR t 1.0 ODH Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet A-2 Speed Grade A-3 Speed Grade Max Min 2.0 0.0 0.9 0.0 0.6 0.4 0.4 0.9 1.6 4.0 4.0 0.4 0.4 1.1 1.1 0.6 0.6 A-2 Speed Grade A-3 Speed Grade ...
Page 48
FLEX 8000 Programmable Logic Device Family Data Sheet EPF81500A Internal Timing Parameters EPF81500A I/O Element Timing Parameters A-2 Speed Grade Symbol Min t IOD t IOC t IOE t IOCO t IOCOMB t 1.4 IOSU t 0.0 IOH t IOCLR ...
Page 49
EPF81500A LE Timing Parameters A-2 Speed Grade Symbol Min t LUT t CLUT t RLUT t GATE t CASC t CICO t CGEN t CGENR 4 4 COMB t 0.8 SU ...
Page 50
FLEX 8000 Programmable Logic Device Family Data Sheet Power Consumption 50 The supply power for FLEX 8000 devices, P, can be calculated with the following equation [(I INT IO CC STANDBY Typical I values ...
Page 51
Configuration & Operation f Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 20. FLEX 8000 I CC ACTIVE 5.0-V FLEX 8000 Devices 1,000 800 600 400 200 0 3.3-V FLEX 8000 Devices 100 ...
Page 52
FLEX 8000 Programmable Logic Device Family Data Sheet 52 Operating Modes The FLEX 8000 architecture uses SRAM elements that require configuration data to be loaded whenever the device powers up and begins operation. The process of physically loading the SRAM ...
Page 53
Device Tables 15 pins in each FLEX 8000 device package. Pin-Outs Table 15. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs (Part Pin Name 84-Pin PLCC EPF8282A (2) 75 nSP (2) 74 MSEL0 (2) 53 MSEL1 ...
Page 54
FLEX 8000 Programmable Logic Device Family Data Sheet Table 15. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs (Part Pin Name 84-Pin PLCC EPF8282A 78 ADD0 3 DATA7 4 DATA6 6 DATA5 7 DATA4 8 DATA3 ...
Page 55
Table 15. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs (Part Pin Name 84-Pin PLCC EPF8282A 5, 26, 47 26, 47, GND No Connect – (N.C.) Total User I/O 64 Pins Altera Corporation FLEX ...
Page 56
... Altera Corporation 208-Pin PQFP EPF81188A ( 124 107 154 138 118 121 137 142 144 128 134 ...
Page 57
... PQFP EPF81188A (1) 172 170 168 166 163 161 119 – – – – – ...
Page 58
... ADD7 G11 ADD6 F14 ADD5 E13 ADD4 D15 ADD3 D14 ADD2 E12 ADD1 C15 ADD0 A7 DATA7 D7 DATA6 A6 DATA5 A5 DATA4 58 232-Pin 240-Pin PGA PQFP EPF81188A EPF81188A C14 237 G15 21 L15 40 L3 141 R4 117 C4 184 G3 160 P1 133 N1 137 G2 158 E2 166 E3 169 K2 146 H2 155 ...
Page 59
... G8, G9, G10, H1, H4, H5, H6, H7, H8, H9, H10, H11, J6, J7, J8, J9, J10, K6, K7, K8, K9, K11, L15, N3, P1 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet 232-Pin 240-Pin PGA PQFP EPF81188A EPF81188A D7 196 B5 194 A3 191 A2 189 N2 135 – – – – – ...
Page 60
... TRST must be grounded. TMS, TDI, and TCK should be tied to V Revision History 60 232-Pin 240-Pin PGA PQFP EPF81188A EPF81188A – 61, 62, 119, 120, 181, 182, 239, 240 180 180 in this data book for more information. The information contained in the FLEX 8000 Programmable Logic Device Family Data Sheet version 9 ...
Page 61
FLEX 8000 Programmable Logic Device Family Data Sheet ® Altera, MAX, MAX+PLUS, MAX+PLUS II, AHDL, FLEX, FLEX 8000, FastTrack Interconnect, and specific 101 Innovation Drive device designations are trademarks and/or service marks of Altera Corporation in the United States and ...