MK60N256VLL100 FREESCALE [Freescale Semiconductor, Inc], MK60N256VLL100 Datasheet - Page 45

• Manufacturer Part Number: MK60N256VLL100
• Description: Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

1. Typical values assume V
2. ADC must be configured to use the internal voltage reference (VREFOUT)
3. PGA reference connected to the VREFOUT pin. If the user wishes to drive VREFOUT with a voltage other than the output
4. For single ended configurations the input impedence of the driven input is 1/2.
5. The analog source resistance (R
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
6.6.1.4 16-bit ADC with PGA characteristics
Freescale Semiconductor, Inc.
I
Symbol
Symbol
I
DDA_PGA
R
DC_PGA
PSRR
reference only and are not tested in production.
of the VREF module, the VREF module must be disabled.
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
time should be allowed for F
8 MHz ADC clock.
R
I
PGAD
BW
T
ILKG
G
AS
S
Differntial input
impedance
Analog source
resistance
ADC sampling
time
Description
Supply current
Input DC current
Input Leakage
current
Gain
Input signal
bandwidth
Power supply
rejection ration
Description
Table 26. 16-bit ADC with PGA operating conditions (continued)
4
DDA
Table 27. 16-bit ADC with PGA characteristics
K60 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
in
Gain = 1, 2, 4, 8
Gain = 16, 32
Gain = 64
Conditions
= 3.0 V, Temp = 25°C, f
=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
PGA disabled
Gain=1
Conditions
AS
• PGAG=0
• PGAG=1
• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
• PGAG=6
• 16-bit modes
• < 16-bit modes
), external to MCU, should be kept as minimum as possible. Increased R
Table continues on the next page...
Preliminary
ADCK
1.25
Min.
—
—
—
—
= 6 MHz unless otherwise stated. Typical values are for
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Min.
—
—
—
—
Typ.
Peripheral operating requirements and behaviors
128
100
64
32
—
1
Typ.
TBD
TBD
0.98
1.99
3.97
7.95
15.8
31.4
61.2
590
—
—
1
Max.
—
—
—
—
—
Max.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
40
—
4
Unit
kΩ
µs
Ω
Unit
kHz
kHz
μA
μA
dB
A
AS
f
IN+ to IN-
R
VDDA
V
±100mV,
AS
causes drop
Notes
DDA
Notes
60Hz
5
6
< 100Ω
= 50Hz,
2
3
= 3V
4
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