KSZ8842-16MBL-EVAL MICREL [Micrel Semiconductor], KSZ8842-16MBL-EVAL Datasheet - Page 101

• Manufacturer Part Number: KSZ8842-16MBL-EVAL
• Description: 2-Port Ethernet Switch with Non-PCI Interface
• Manufacturer: MICREL [Micrel Semiconductor]

Bank 48 Port 1 VID Control Register (0x04): P1VIDCR
This register contains the global per port control for the switch function.
Note: This VID Control register serves two purposes:
1. Associated with the ingress untagged packets, and used for egress tagging.
2. Default VID for the ingress untagged or null-VID-tagged packets, and used for address lookup.
Bank 48 Port 1 Control Register 3 (0x06): P1CR3
Micrel, Inc.
Bit
15-13
12
11-0
Bit
15-5
4
3-2
1
0
October 2007
Default
0
Default
0x0
0
0
0x0
0x001
0x000
0x0
R/W
RW
RW
RW
R/W
RO
RW
RW
RW
RW
Description
Default Tag[15:13]
Port’s default tag, containing “User Priority Field” bits.
Default Tag[12]
Port’s default tag, containing CFI bit.
Default Tag[11:0]
Port’s default tag, containing VID[11:0].
Description
Reserved
Reserved
Ingress Limit Mode
These bits determine what kinds of frames are limited and counted against Ingress
limiting as follows:
00 = Limit and count all frames.
01 = Limit and count Broadcast, Multicast, and flooded unicast frames.
10 = Limit and count Broadcast and Multicast frames only.
11 = Limit and count Broadcast frames only.
Count IFG
Count IFG Bytes.
1= each frame’s minimum inter frame gap.
(IFG) bytes (12 per frame) are included in Ingress and Egress rate limiting
calculations.
0= IFG bytes are not counted.
Count Preamble
Count preamble Bytes.
1 = each frame’s preamble bytes (8 per frame) are included in Ingress and Egress rate
limiting calculations.
0 = preamble bytes are not counted.
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KSZ8842-16/32 MQL/MVL/MVLI/MBL
M9999-102207-1.9