PIC12F635-E/MD MICROCHIP [Microchip Technology], PIC12F635-E/MD Datasheet - Page 38
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PIC12F635-E/MD
Manufacturer Part Number
PIC12F635-E/MD
Description
8/14-Pin, Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC12F635-EMD.pdf
(234 pages)
- Current page: 38 of 234
- Download datasheet (5Mb)
PIC12F635/PIC16F636/639
3.2
The Oscillator Control (OSCCON) register (Figure 3-1)
controls the system clock and frequency selection
options. The OSCCON register contains the following
bits:
• Frequency selection bits (IRCF)
• Frequency Status bits (HTS, LTS)
• System clock control bits (OSTS, SCS)
REGISTER 3-1:
DS41232D-page 36
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
Note 1:
U-0
—
Oscillator Control
Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe
mode is enabled.
Unimplemented: Read as ‘0’
IRCF<2:0>: Internal Oscillator Frequency Select bits
111 = 8 MHz
110 = 4 MHz (default)
101 = 2 MHz
100 = 1 MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (LFINTOSC)
OSTS: Oscillator Start-up Time-out Status bit
1 = Device is running from the external clock defined by FOSC<2:0> of the Configuration Word
0 = Device is running from the internal oscillator (HFINTOSC or LFINTOSC)
HTS: HFINTOSC Status bit (High Frequency – 8 MHz to 125 kHz)
1 = HFINTOSC is stable
0 = HFINTOSC is not stable
LTS: LFINTOSC Stable bit (Low Frequency – 31 kHz)
1 = LFINTOSC is stable
0 = LFINTOSC is not stable
SCS: System Clock Select bit
1 = Internal oscillator is used for system clock
0 = Clock source defined by FOSC<2:0> of the Configuration Word
IRCF2
R/W-1
OSCCON: OSCILLATOR CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
R/W-1
IRCF1
IRCF0
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(1)
OSTS
R-1
(1)
HTS
R-0
© 2007 Microchip Technology Inc.
x = Bit is unknown
LTS
R-0
R/W-0
SCS
bit 0
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