SPC5125YVN400 FREESCALE [Freescale Semiconductor, Inc], SPC5125YVN400 Datasheet
SPC5125YVN400
Related parts for SPC5125YVN400
SPC5125YVN400 Summary of contents
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Freescale Semiconductor Data Sheet: Technical Data MPC5125 Microcontroller Data Sheet The MPC5125 integrates a high performance e300 CPU core based on the Power Architecture™ Technology with a rich set of peripheral functions focused on communications and systems integration. Major features ...
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Ordering Information MPC5125 Block Diagrams . ...
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Ordering Information Operating frequency (MHz) Tape and reel status Temperature Range Package Identifier Y = –40 °C to 125 ° 324 TEPBGA Pb-free junction Note: Not all options are available on all devices. Refer to Figure 1. ...
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MPC5125 Block Diagrams 2 MPC5125 Block Diagrams Figure 2 shows a simplified MPC5125 block diagram. Functionally Multiplexed I/O LPC NFC TempSensor Fuse PMC JTAG/COP JTAG/COP Clock/Reset Figure 2. Simplified MPC5125 Block Diagram 4 Display SDR, Mobile DDR, DDR1/2 Memory DIU ...
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Pin Assignments This section details pin assignments. 3.1 324-ball TEPBGA Pin Assignments Figure 3 shows the 324-ball TEPBGA pin assignments EMB_A EMB_A A VSS VSS GPIO01 GPIO02 D01 D00 EMB_A EMB_A EMB_A J1850_ ...
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Pin Muxing and Reset States Table 2 provides the pinout listing for the MPC5125. Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset GPIO00 — ALT0 GPIO00 ALT1 — ALT2 — ALT3 — GPIO01 — ALT0 ...
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Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset SPLL_ANAVIZ — ALT0 SPLL_ANAVIZ ALT1 — ALT2 — ALT3 — TMPS_ANAVIZ — ALT0 TMPS_ANAVIZ ALT1 — ALT2 — ALT3 — SYS_XTALI — ALT0 SYS_XTALI ALT1 — ALT2 — ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MVTT0 — ALT0 MVTT0 ALT1 — ALT2 — ALT3 — MVTT1 — ALT0 MVTT1 ALT1 — ALT2 — ALT3 — MVTT2 — ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MDQ03 0x00 ALT0 MDQ03 IO_CON- ALT1 — TROL_MEM ALT2 — ALT3 — MDQ04 0x00 ALT0 MDQ04 IO_CON- ALT1 — TROL_MEM ALT2 — ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MDQ11 0x00 ALT0 MDQ11 IO_CON- ALT1 — TROL_MEM ALT2 — ALT3 — MDQ12 0x00 ALT0 MDQ12 IO_CON- ALT1 — TROL_MEM ALT2 — ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MDQ19 0x00 ALT0 MDQ19 ALT1 — IO_CON- ALT2 — TROL_MEM ALT3 GPT1[3] MDQ20 0x00 ALT0 MDQ20 ALT1 — IO_CON- ALT2 — TROL_MEM ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MDQ27 0x00 ALT0 MDQ27 ALT1 — IO_CON- ALT2 — TROL_MEM ALT3 GPIO24 MDQ28 0x00 ALT0 MDQ28 ALT1 — IO_CON- ALT2 — TROL_MEM ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MDM3 0x00 ALT0 MDM3 ALT1 — IO_CON- ALT2 — TROL_MEM ALT3 GPIO30 MDQS0 0x00 ALT0 MDQS0 ALT1 — IO_CON- ALT2 — TROL_MEM ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MA00 0x00 ALT0 MA00 ALT1 — IO_CON- ALT2 — TROL_MEM ALT3 — MA01 0x00 ALT0 MA01 ALT1 — IO_CON- ALT2 — TROL_MEM ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MA08 0x00 ALT0 MA08 ALT1 — IO_CON- ALT2 — TROL_MEM ALT3 — MA09 0x00 ALT0 MA09 ALT1 — IO_CON- ALT2 — TROL_MEM ...
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Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MCK 0x00 ALT0 MCK ALT1 — IO_CON- ALT2 — TROL_MEM ALT3 — MCK 0x00 ALT0 MCK ALT1 — IO_CON- ALT2 — TROL_MEM ALT3 — MCKE 0x00 ALT0 MCKE ...
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Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset LPC_ACK_B 0x08 ALT0 LPC_ACK/LPC_BURST ALT1 NFC_CE1 STD_PU ALT2 LPC_CS1 ALT3 GPIO08 LPC_AX03 0x09 ALT0 LPC_AX03/LPC_TS ALT1 NFC_CE2 STD_PU ALT2 LPC_CS2 ALT3 — EMB_AD00 0x2C ALT0 LPC_AD00/NFC_AD00 ALT1 — ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset EMB_AD05 0x27 ALT0 LPC_AD05/NFC_AD05 ALT1 — STD_PU ALT2 RST_CONF_COREPLL6 ALT3 — EMB_AD06 0x26 ALT0 LPC_AD06/NFC_AD06 ALT1 — STD_PU ALT2 RST_CONF_COREPLL5 ALT3 — ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset EMB_AD13 0x1F ALT0 LPC_AD13/NFC_AD13 ALT1 PSC2_2 STD_PU ALT2 RST_CONF_PREDIV1 ALT3 GPIO23 EMB_AD14 0x1E ALT0 LPC_AD14/NFC_AD14 ALT1 PSC2_1 STD_PU ALT2 RST_CONF_PREDIV2 ALT3 GPIO22 ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset EMB_AD21 0x17 ALT0 LPC_AD21/LPC_A06 ALT1 — STD_PU ALT2 — ALT3 GPIO19 EMB_AD22 0x16 ALT0 LPC_AD22/LPC_A07 ALT1 — STD_PU ALT2 RST_CONF_LPC_TS ALT3 GPIO18 ...
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Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset EMB_AD29 0x0F ALT0 LPC_AD29/LPC_A14 ALT1 — STD_PU ALT2 — ALT3 GPIO11 EMB_AD30 0x0E ALT0 LPC_AD30/LPC_A15 ALT1 CAN_CLK STD_PU_ST ALT2 — ALT3 GPIO10 EMB_AD31 0x0D ALT0 LPC_AD31/LPC_A16 ALT1 PSC_MCLK_IN ...
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Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset DIU_CLK 0x02F ALT0 DIU_CLK ALT1 PSC4_0 STD_PU ALT2 USB1_DATA0 ALT3 LPC_AX04 DIU_DE 0x030 ALT0 DIU_DE ALT1 PSC4_1 STD_PU ALT2 USB1_DATA1 ALT3 LPC_AX05 DIU_HSYNC 0x031 ALT0 DIU_HSYNC ALT1 PSC4_2 ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset DIU_LD04 0x037 ALT0 DIU_LD04 ALT1 PSC5_1 STD_PU ALT2 USB1_DATA6 ALT3 LPC_AX09 DIU_LD05 0x038 ALT0 DIU_LD05 ALT1 PSC5_2 STD_PU ALT2 USB1_DATA7 ALT3 GPIO34 ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset DIU_LD12 0x03F ALT0 DIU_LD12 ALT1 PSC6_4 STD_PU ALT2 USB2_DATA0 ALT3 GPT2[0] DIU_LD13 0x040 ALT0 DIU_LD13 ALT1 PSC7_0 STD_PU ALT2 USB2_DATA1 ALT3 GPT2[1] ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset DIU_LD20 0x047 ALT0 DIU_LD20 ALT1 PSC8_0 STD_PU ALT2 USB2_DATA6 ALT3 GPT2[6] DIU_LD21 0x048 ALT0 DIU_LD21 ALT1 PSC8_1 STD_PU ALT2 USB2_DATA7 ALT3 GPT2[7] ...
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Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset CAN1_RX — ALT0 CAN1_RX ALT1 — ALT2 — ALT3 — CAN2_RX — ALT0 CAN2_RX ALT1 — ALT2 — ALT3 — CAN1_TX 0x4D ALT0 CAN1_TX ALT1 PSC9_0 STD_PU_ST ALT2 ...
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Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset FEC1_CRS 0x55 ALT0 FEC1_CRS ALT1 PSC2_4 STD_PU ALT2 USB2_DATA4 ALT3 GPIO55 FEC1_TX_ER 0x56 ALT0 FEC1_TX_ER ALT1 PSC3_0 STD_PU ALT2 USB2_DATA5 ALT3 GPIO56 FEC1_RXD_1 0x57 ALT0 FEC1_RXD_1/RMII_RX1 ALT1 PSC3_1 ...
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Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset FEC1_TXD_0 0x5D ALT0 FEC1_TXD_0/RMII_TX0 ALT1 — STD_PU_ST ALT2 NFC_R/B1 ALT3 GPIO63 FEC1_TX_CLK 0x5E ALT0 FEC1_TX_CLK/RMII_REF_CLK ALT1 PSC0_0 STD_PU_ST ALT2 — ALT3 GPIO04 FEC1_RX_CLK 0x5F ALT0 FEC1_RX_CLK ALT1 PSC0_1 ...
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Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset USB1_DATA2 0x65 ALT0 USB1_DATA2 ALT1 PSC1_2 STD_PU ALT2 FEC2_MDC/RMII_MDC ALT3 — USB1_DATA3 0x66 ALT0 USB1_DATA3 ALT1 PSC1_3 STD_PU ALT2 FEC2_RX_ER/RMII_RX_ER ALT3 — USB1_DATA4 0x67 ALT0 USB1_DATA4 ALT1 PSC1_4 ...
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Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset USB1_NEXT 0x6D ALT0 USB1_NEXT ALT1 — STD_PU ALT2 FEC2_TX_EN/RMII_TX_EN ALT3 GPIO09 USB1_DIR 0x6E ALT0 USB1_DIR ALT1 — STD_PU_ST ALT2 FEC2_COL ALT3 GPIO10 SDHC1_CLK 0x6F ALT0 SDHC1_CLK ALT1 NFC_CE1 ...
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Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset PSC_MCLK_IN 0x75 ALT0 PSC_MCLK_IN ALT1 — STD_PU_ST ALT2 — ALT3 GPIO14 PSC0_0 0x76 ALT0 PSC0_0 ALT1 SDHC2_CMD STD_PU ALT2 GPT1[0] ALT3 GPIO15 PSC0_1 0x77 ALT0 PSC0_1 ALT1 SDHC2_D0 ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset PSC1_2 0x7D ALT0 PSC1_2 ALT1 TPA2 STD_PU ALT2 GPT1[7] ALT3 IRQ1 PSC1_3 0x7E ALT0 PSC1_3 ALT1 CKSTP_IN STD_PU ALT2 NFC_R/B2 ALT3 GPIO19 ...
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Table 2. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset TMS — ALT0 TMS ALT1 — ALT2 — ALT3 — TRST — ALT0 TRST ALT1 — ALT2 — ALT3 — HRESET — ...
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Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset TEST — ALT0 TEST ALT1 — ALT2 — ALT3 — NOTES: 1 Pins controlled by the STD_PU_ST register have a Schmitt trigger input; pins controlled by the STD_PU ...
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Power and Ground Supply Summary Table 3. MPC5125 324 TEPBGA Power/Ground Pin Name V Supply voltage — e300 core and peripheral logic DD V Supply voltage — I/O buffers DD_IO V Supply voltage — memory DD_IO_MEM AV DD_FUSEWR AV ...
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Electrical and Thermal Characteristics 4 Electrical and Thermal Characteristics 4.1 DC Electrical Characteristics 4.1.1 Absolute Maximum Ratings The tables in this section describe the MPC5125 DC electrical characteristics. Characteristic Supply voltage — e300 core and peripheral logic Supply voltage — ...
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Table 5. Recommended Operating Conditions (continued) Characteristic Supply voltage — standard buffers Supply voltage — memory buffers (DDR) Supply voltage — memory I/O buffers (DDR2, LPDDR, Mobile SDR) Supply voltage — memory I/O buffers ...
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Electrical and Thermal Characteristics Table 6. DC Electrical Specifications (continued) Characteristic Condition Input high voltage Input type = TTL V DD_IO_MEM_DDR2 Input high voltage Input type = TTL V DD_IO_MEM_LPDDR Input high voltage Input type = TTL V DD_IO_MEM_SDR Input ...
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Table 6. DC Electrical Specifications (continued) Characteristic Condition Output high voltage IOH is driver dependent V DD_IO_MEM_SDR Output low voltage IOL is driver dependent Output low voltage IOL is driver dependent V DD_IO_MEM_DDR Output low voltage IOL is driver dependent ...
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Electrical and Thermal Characteristics Table 7. General I/O Pads Pad Type Supply Voltage General 3.3 V DD_IO NOTES: 1 General I/O—rise and fall times at drive load 50 pF. 1 Table 8. DDR I/O Pads Pad Type ...
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Power Dissipation Power dissipation of the MPC5125 is caused by three different components: • Dissipation of the internal or core digital logic (supplied by V • Dissipation of the analog circuitry (supplied by AV • Dissipation of the IO ...
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Electrical and Thermal Characteristics 3 Doze, Nap, and Sleep power are measured with the e300 core in Doze/Nap/Sleep mode; the system oscillator, system PLL, and core PLL active; and all other system modules inactive. 4 Deep-sleep power is measured with ...
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The junction to ambient thermal resistance is an industry standard value, which provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single-layer board, and the value obtained ...
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Electrical and Thermal Characteristics • The system PLL (SYS_PLL) takes an external reference frequency and generates the internal system clock. The system clock frequency is determined by the external reference frequency and the settings of the SYS_PLL configuration. • The ...
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System PLL Electrical Characteristics Characteristic 1 Sys PLL input clock frequency 2 Sys PLL input clock jitter 1 Sys PLL VCO frequency Sys PLL VCO output jitter (Dj), peak to peak / cycle Sys PLL VCO output jitter (Rj), ...
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Electrical and Thermal Characteristics 4.3 AC Electrical Characteristics 4.3.1 Overview The following list provides hyperlinks to the indicated timing specification sections. • AC Operating Frequency Data • Resets • SDRAM (DDR) • LPC • NFC • FEC • USB ULPI ...
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The SYS_XTAL_IN frequency, Sys PLL, and Core PLL settings must be chosen so that the resulting e300 clk, csb_clk, and MCK frequencies do not exceed their respective maximum or minimum operating frequencies. 2. The values are valid for the ...
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Electrical and Thermal Characteristics XTALI CLOCK PORESET HRESET SRESET t S_POR_CONF RST_CONF[31:0] ADDR[31:0] XTALI CLOCK PORESET HRESET SRESET RST_CONF[31:0] ADDR[31: HRVAL t SRVAL t EXEC t H_POR_CONF Figure 5. Power-Up Behavior t PORHold t HRVAL t S_POR_CONF t ...
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XTALI CLOCK PORESET HRESET SRESET RST_CONF[31:0] ADDR[31:0] XTALI CLOCK PORESET HRESET SRESET RST_CONF[31:0] ADDR[31:0] Symbol t Time PORESET must be held low before a qualified reset occurs. PORHOLD t Time HRESET is asserted after a qualified reset occurs. HRVAL t ...
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Electrical and Thermal Characteristics Symbol t Reset configuration hold time after assertion of PORESET. H_POR_CONF t Time from falling edge of HRESET to falling edge of SRESET. HR_SR_DELAY t Time HRESET must be held low before a qualified reset occurs. ...
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DDR SDRAM AC Timing Specifications Table 21. DDR SDRAM Timing Specifications At recommended operating conditions with V Parameter Clock cycle time MCK AC differential crosspoint voltage CK HIGH pulse width CK LOW pulse width Skew between ...
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Electrical and Thermal Characteristics Table 22. MobileDDR/LPDDR SDRAM Timing Specifications (continued) At recommended operating conditions with V Parameter Address and control output hold time relative to MCK rising edge DQ and DM output setup time relative to DQS DQ and ...
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NOTES: Measured with clock pin loaded with differential 100 Ω termination resistor. 1 Measured with all outputs except the clock loaded with 50 Ω termination resistor All transitions measured at mid-supply ( this window, ...
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Electrical and Thermal Characteristics Figure 10 and Figure 11 show the DDR SDRAM read timing. DQS(in) Any DQ(in) MCK Command Address DQS(in) Figure 12 shows the SDR AC timing. MCK Output Input Figure 13 provides the AC test load for ...
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LPC The local-plus bus is the external bus interface of the MPC5125. A maximum of eight configurable chip selects (CS) are provided. There are two main modes of operation: non-MUXed and MUXed. The reference clock is the LPC CLK. ...
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Electrical and Thermal Characteristics Sym Description t Non-MUXed mode page burst: ADDR cycle 19 t Non-MUXed mode page burst: burst DATA 20 (rd) input setup before next ADDR cycle t Non-MUXed mode page burst: burst DATA 21 (rd) input hold ...
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ACK is asynchronous input signal and has no timing requirements. ACK needs to be deasserted after CS[x] is deasserted. 4.3.6.1.2 Non-MUXed Synchronous Read Burst Mode LPC_CLK t CS[x] 2 ADDR TS OE R/W DATA (rd) ACK Figure 15. Timing Diagram ...
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Electrical and Thermal Characteristics 4.3.6.1.4 Non-MUXed Asynchronous Read Burst Mode (Page Mode) LPC_CLK CS[ ADDR[31:n+1] ADDR[n: R/W DATA (rd) ACK Figure 17. Timing Diagram — Non-MUXed Asynchronous Read Burst 4.3.6.1.5 Non-MUXed Asynchronous Write Burst Mode LPC_CLK ...
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MUXed Mode 4.3.6.2.1 MUXed Non-Burst Mode LPC_CLK AD[31:0] (wr) Address AD[31:0] (rd) Address R ALE TS CS[x] OE ACK TSIZ[1:0] Figure 19. Timing Diagram — MUXed non-Burst Mode ACK is asynchronous input signal and has no timing ...
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Electrical and Thermal Characteristics 4.3.6.2.2 MUXed Synchronous Read Burst Mode LPC_CLK t AD[31:0] (rd) Address t 18 ALE TS CS[x] OE R/W ACK Figure 20. Timing Diagram — MUXed Synchronous Read Burst 4.3.6.2.3 MUXed Synchronous Write Burst Mode LPC_CLK AD[31:0] ...
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NFC The NAND flash controller (NFC) implements the interface to standard NAND flash memory devices. This section describes the timing parameters of the NFC the flash clock high time flash clock low time, where Refer ...
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Electrical and Thermal Characteristics NFC_CLE NFC_CE[3:0] NFC_WE NFIO[7:0] NFC_ALE NFC_CE[3:0] NFC_WE NFIO[7: NFC_CE[3:0] NFC_WE NFIO[15: CLS command t DS Figure 22. Command Latch Cycle Timing t ALS address ...
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NFC_CE[3:0] NFC_RE NFIO[15: NFC_RB Figure 25. Read Data Latch Timing in Non-Fast Mode NFC_CE[3:0] NFC_RE NFIO[15: NFC_RB Figure 26. Read Data Latch Timing in Fast Mode 4.3.8 FEC AC test timing conditions: • Output Loading All ...
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Electrical and Thermal Characteristics Sym Description t RXD [ RX_DV, RX_ER to TX_CLK setup 5 t TX_CLK to RXD [ RX_DV, RX_ER hold 6 t TX_CLK pulse width high 7 t TX_CLK ...
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TX_CLK (Input) TXD[3:0] (Outputs) TX_EN TX_ER Figure 28. Ethernet Timing Diagram — MII Tx Signal Sym Description t CRS, COL minimum pulse width 17 Figure 29. Ethernet Timing Diagram — MII Async Table 32. MII Serial Management Channel Signal Timing ...
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Electrical and Thermal Characteristics MDC (Output) MDIO (Output) MDIO (Input) Figure 30. Ethernet Timing Diagram — MII Serial Management 4.3.9 USB ULPI This section specifies the USB ULPI timing. For more information refer to UTMI+ Low Pin Interface (ULPI) Specification, ...
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NOTES: 1 Output timing is specified at a nominal 50 pF load. 4.3.10 MMC/SD/SDIO Card Host Controller (SDHC) Figure 32 depicts the timings of the SDHC. Output from SDHC to card MMCx_DAT_1 Input from card to SDHC MMCx_DAT_1 Table 34 ...
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Electrical and Thermal Characteristics NOTES low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2 normal data transfer mode for SD/SDIO card, clock frequency can be any value ...
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PWH Start of line t PCP DIU_CLK Invalid Data DIU_LD[23:0] DIU_HSYNC DIU_DE Figure 34. TFT LCD Interface Timing Diagram — Horizontal Sync Pulse Figure 35 depicts the vertical timing (timing of one frame), including the vertical sync pulse and ...
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Electrical and Thermal Characteristics Table 35. LCD Interface Timing Parameters — Pixel Level Sym Description t HSYNC Front Porch Width FPH t Screen Width SW t HSYNC (Line) Period HSP t VSYNC Pulse Width PWV t VSYNC Back Porch Width ...
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CAN The CAN functions are available as TX pins at normal IO pads and as RX pins at the VBAT domain. There is no filter for the wakeup dominant pulse. Any high-to-low edge can cause wakeup, if configured. 2 ...
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Electrical and Thermal Characteristics 2 SCL 1 SDA Figure 37. Timing Diagram — I 4.3.14 J1850 See the MPC5125 Reference Manual (MPC5125RM). 4.3.15 PSC The programmable serial controllers (PSC) support different modes of operation (UART, codec, AC97, SPI). All the ...
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BitClk (CLKPOL=0) Output BitClk (CLKPOL=1) Output 5 FrameSync (SyncPol= 1) Output FrameSync (SyncPol= 0) Output TxD Output RxD Input Figure 38. Timing Diagram — 8-,16-, 24-, and 32-bit CODEC/I Table 40. Timing Specifications — 8-,16-, 24-, and 32-bit CODEC/I Sym ...
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Electrical and Thermal Characteristics BitClk (CLKPOL=0) Input BitClk (CLKPOL=1) Input FrameSync (SyncPol= 1) Input FrameSync (SyncPol= 0) Input TxD Output RxD Input Figure 39. Timing Diagram — 8-,16-, 24-, and 32-bit CODEC/I 4.3.15.2 AC97 Mode Table 41. Timing Specifications — ...
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BitClk (CLKPOL=0) 4 Input FrameSync (SyncPol= 1) Output 5 Sdata_out Output 6 Sdata_in Input 4.3.15.3 SPI Mode Table 42. Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0) Sym 1 SCK cycle time, programable in the PSC ...
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Electrical and Thermal Characteristics SCK (CLKPOL=0) Output SCK (CLKPOL=1) Output 3 SS Output 4 MOSI Output 6 MISO Input Figure 41. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0) Table 43. Timing Specifications — SPI Slave Mode, ...
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SCK (CLKPOL=0) Input SCK (CLKPOL=1) Input 3 SS Input 4 MOSI Input 6 MISO Output Figure 42. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0) Table 44. Timing Specifications — SPI Master Mode, Format 1 (CPHA = ...
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Electrical and Thermal Characteristics SCK (CLKPOL=0) Output SCK (CLKPOL=1) Output 3 SS Output 4 MOSI Output MISO Input Figure 43. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1) Table 45. Timing Specifications — SPI Slave Mode, Format ...
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SCK (CLKPOL=0) Input SCK (CLKPOL=1) Input 3 SS Input MOSI Input 4 MISO Output Figure 44. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1) 4.3.16 GPIOs and Timers The MPC5125 contains several sets of I/Os that do ...
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Electrical and Thermal Characteristics 4.3.18 IEEE 1149.1 (JTAG) Sym — TCK frequency of operation 1 TCK cycle time 2 TCK clock pulse width measured at 1 TCK rise and fall times 4 TRST setup time to TCK falling ...
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TCK TRST TCK Data Inputs Data Outputs Data Outputs Figure 47. Timing Diagram — JTAG Boundary Scan TCK TDI, TMS TDO TDO Figure 48. Timing Diagram — Test Access Port Freescale Semiconductor 4 5 Numbers shown reference JTAG Timing Specification ...
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System Design Information 5 System Design Information 5.1 Power Up/Down Sequencing Power sequencing between the 1.4 V power supply V during power-up phase. The required power sequence is as follows: • Use 12 V/ms or slower time for all supplies. ...
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Pullup/Pulldown Resistor Requirements The MPC5125 requires external pullup or pulldown resistors on certain pins. 5.4.1 Pulldown Resistor Requirements for TEST Pin The MPC5125 requires a pulldown resistor on the test pin TEST. 5.5 JTAG The MPC5125 has an IEEE ...
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System Design Information BDM Pin # Pin 16 — 15 CKSTP_OUT 14 — 13 HRESET 12 — 11 SRESET 10 — 9 TMS 8 CKSTP_IN 7 TCK 6 — 5 See Note 4 TRST 3 TDI pci_frame ...
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PORESET COP Header COP Connector Physical Pinout 5.5.2.2 Boards Without COP Connector If the JTAG interface is not used, TRST should ...
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System Design Information PORESET HRESET SRESET Figure 52. TRST Wiring for Boards without COP Connector 86 PORESET HRESET 10 kΩ VDD_IO 10 kΩ VDD_IO SRESET TRST 10 kΩ VDD_IO JTAG_TMS 10 kΩ VDD_IO TCK 10 kΩ VDD_IO TDI CKSTP_OUT TDO ...
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Package Information This section details package parameters and dimensions. The MPC5125 is available in a thermally enhanced plastic ball grid array (TEPBGA). Section 6.1, “Package TEPBGA. 6.1 Package Parameters Package outline Interconnects Pitch Module height (typical) Solder balls Ball ...
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Package Information 6.2 Mechanical Dimensions Figure 3 shows the mechanical dimensions and bottom surface nomenclature of the MPC5125 324 TEPBGA package. Figure 53. Mechanical Drawing of MPC5125 PBGA ( MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor ...
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Figure 54. Mechanical Drawing of MPC5125 PBGA ( Freescale Semiconductor MPC5125 Microcontroller Data Sheet, Rev. 3 Package Information 89 ...
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Package Information Figure 55. Mechanical Drawing of MPC5125 PBGA ( MPC5125 Microcontroller Data Sheet, Rev. 3 Freescale Semiconductor ...
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Product Documentation This data sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these types are available at: http://www.freescale.com . The following documents are required for a complete description of the device ...
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How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter ...