CP80S54E ETC2 [List of Unclassifed Manufacturers], CP80S54E Datasheet - Page 14

• Manufacturer Part Number: CP80S54E
• Description: EPROM/ROM-Based 8-Bit Microcontroller Series
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

2.1.16 OPTION Register
Accessed by OPTION instruction.
By executing the OPTION instruction, the contents of the ACC Register will be transferred to the OPTION Register.
The OPTION Register is a 7-bit wide, write-only register which contains various control bits to configure the
Timer0/WDT prescaler, Timer0, and the external INT interrupt.
The OPTION Register are “write-only” and are set all “1”s except INTEDG bit.
PS2:PS0 : Prescaler rate select bits.
PSA : Prescaler assign bit.
T0SE : TMR0 source edge select bit.
T0CS : TMR0 clock source select bit.
INTEDG : Interrupt edge select bit.
Bit7 : Not used.
2.1.17 IOSTA, & IOSTB (Port I/O Control Registers)
Accessed by IOST instruction.
The Port I/O Control Registers are loaded with the contents of the ACC Register by executing the IOST R (05h~06h)
instruction. A ‘1’ from a IOST Register bit puts the corresponding output driver in hi-impedance state (input mode).
A ‘0’ enables the output buffer and puts the contents of the output data latch on the selected pins (output mode).
The IOST Registers are “write-only” and are set (output drivers disabled) upon RESET.
Address
Address
N/A (w)
N/A (w)
N/A (w)
= 1, WDT (watch-dog timer).
= 0, TMR0 (Timer0).
= 1, Falling edge on T0CKI pin.
= 0, Rising edge on T0CKI pin.
= 1, External T0CKI pin.
= 0, internal instruction clock cycle.
= 1, interrupt on rising edge of INT pin.
= 0, interrupt on falling edge of INT pin.
OPTION
IOSTB
IOSTA
Name
Name
PS2:PS0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
B7
B7
-
INTEDG
B6
Timer0 Rate
B6
1:128
1:256
1:16
1:32
1:64
1:2
1:4
1:8
T0CS
B5
B5
Port B I/O Control Register
Port A I/O Control Register
T0SE
B4
B4
WDT Rate
1:128
1:16
1:32
1:64
1:1
1:2
1:4
1:8
PSA
B3
B3
CP80S54/56
PS2
B2
B2
PS1
Rev0.1 Nov 30, 2005
B1
B1
P.14/CP80S54/S56
PS0
B0
B0