AT22V10B-10DI ATMEL [ATMEL Corporation], AT22V10B-10DI Datasheet - Page 6

• Manufacturer Part Number: AT22V10B-10DI
• Description: High Speed UV Erasable Programmable Logic Device
• Manufacturer: ATMEL [ATMEL Corporation]

Power Up Reset
The registers in the AT22V10B are designed to reset during
power up. At a point delayed slightly from V
all registers will be reset to the low state. The output state will
depend on the polarity of the output buffer.
This feature is critical for state machine initialization. However,
due to the asynchronous nature of reset and the uncertainty of
how V
are required:
1) The V
2) After reset occurs, all input and feedback setup times must be
met before driving the clock pin high, and
3) The clock must remain stable during t
Pin Capacitance
Note:
Erasure Characteristics
The entire fuse array of an AT22V10B is erased after exposure
to ultraviolet light at a wavelength of 2537 Å. Complete erasure
is assured after a minimum of 20 minutes exposure using 12,000
Minimum erase time for lamps at other intensity ratings can be
1-114
Preload of Registered Outputs
The registers in the AT22V10B are provided with circuitry to
allow loading of each register asynchronously with either a high
or a low. This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A V
independent of the polarity bit (C0) setting. The preload state is
entered by placing an 10.5-V to 12-V signal on pin 8 on DIPs,
and pin 10 on SMPs. When the clock pin is pulsed high, the data
on the I/O pins is placed into the ten registers.
on the I/O pin will force the register high; a V
W/cm
C
C
IN
OUT
PRELOAD
CLOCK
REGISTERED
OUTPUTS
CC
2
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
intensity lamps spaced one inch away from the chip.
CC
actually rises in the system, the following conditions
rise must be monotonic,
VH
PRELOAD ENA.
OUTPUTS DIS.
AT22V10B
(f = 1 MHz, T = 25°C)
tD
PR
FORCE I/O’S
TO VIH ORVIL
.
Typ
IL
CC
5
6
will force it low,
tD
crossing 3.8 V,
IH
PRELOAD DATA
CLOCKED IN
level
(1)
tD
Max
calculated from the minimum integrated erasure dose of 15
W sec/cm
is recommended to cover the clear window on any UV erasable
PLD which will be subjected to continuous fluorescent indoor
lighting or sunlight.
Parameter
8
8
POWER
REGISTERED
OUTPUTS
CLOCK
t
Level forced on
registered output pin
during preload cycle
PR
2
. To prevent unintentional erasure, an opaque label
tD
3.8 V
V
V
Description
Power-Up
Reset Time
IH
IL
OUTPUT
VOLTAGE
REMOVED
Units
pF
pF
tD
tPR
Min
PRELOAD
DISABLED
Conditions
V
V
Typ
600
Register state
after cycle
IN
OUT
t
High
Low
DMIN
tW
= 0 V
= 0 V
tS
1000
Max Units
= 100 ns
ns