MC68HC11F1MFN2 FREESCALE [Freescale Semiconductor, Inc], MC68HC11F1MFN2 Datasheet - Page 50

• Manufacturer Part Number: MC68HC11F1MFN2
• Description: Technical Summary 8-Bit Microcontroller
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

10.2 SPI Registers
SPCR — SPI Control Register
SPIE — SPI Interrupt Enable
SPE — SPI Enable
DWOM — Port D Wired-OR Mode Option for SPI Pins PD[5:2]
MSTR — Master Mode Select
CPOL — Clock Polarity
CPHA — Clock Phase
50
RESET:
(CPHA = 0) DATA OUT
(CPHA = 1) DATA OUT
(FOR REFERENCE)
U = Unaffected by reset
When SPI interrupts are enabled, a hardware interrupt sequence is requested each time the SPIF or
MODF status flag is set. SPI interrupts are inhibited if this bit is cleared or if the I bit in the condition code
register is one.
When the SPE bit is set, PD[5:2] are dedicated to the SPI function. If the SPI is in master mode and the
DDRD bit 5 is set, then PD5/SS becomes a general-purpose output instead of the SS input.
When the clock polarity bit is cleared and data is not being transferred, the SCK pin of the master device
has a steady state low value. When CPOL is set, SCK idles high. Refer to Figure 13.
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between mas-
ter and slave. The CPHA bit selects one of two clocking protocols. Refer to Figure 13.
SAMPLE INPUT
SAMPLE INPUT
SCK (CPOL = 0)
SCK (CPOL = 1)
SS (TO SLAVE)
0 = SPI interrupt disabled
1 = SPI interrupt enabled
0 = SPI off
1 = SPI on
0 = Normal CMOS outputs
1 = Open-drain outputs
0 = Slave mode
1 = Master mode
SCK CYCLE #
SPIE
Bit 7
0
SPE
6
0
MSB
Freescale Semiconductor, Inc.
For More Information On This Product,
MSB
Figure 13 SPI Data Clock Timing Diagram
1
DWOM
6
5
0
Go to: www.freescale.com
2
6
5
MSTR
4
0
3
5
4
CPOL
4
4
3
0
3
5
3
CPHA
2
1
2
6
2
1
SPR1
U
1
7
1
LSB
MC68HC11F1/FC0
SPR0
MC68HC11FTS/D
Bit 0
LSB
8
U
$x028