LM4546AVH NSC [National Semiconductor], LM4546AVH Datasheet - Page 23

• Manufacturer Part Number: LM4546AVH
• Description: AC 97 Rev 2 Multi-Channel Audio Codec with Sample Rate Conversion and National 3D Sound
• Manufacturer: NSC [National Semiconductor]

Hz increments, to be any value from 4 kHz to 48 kHz. The
value required is the hexadecimal representation of the de-
sired sample rate, e.g. 8000
most common sample rates and the corresponding register
(hex) values.
VENDOR ID REGISTERS (7Ch – 7Eh)
These two read-only (4E53h, 4350h) registers contain
National's Vendor ID and National's LM45xx codec version
Low Power Modes
The LM4546A provides 6 bits to control the powerdown state
of internal analog and digital subsections and clocks. These
6 bits (PR0 – PR5) are located in the 8 MSBs of the Power-
down Control/Status register, 26h. The status of the four main
analog subsections is given by the 4 LSBs in the same reg-
ister, 26h.
The powerdown bits are implemented in compliance with AC
'97 Rev 2 to support the standard device power management
states D0 – D3 as defined in the ACPI and PCI Bus Power
Management specification.
PR0 controls the powerdown state of the ADC and associated
sampling rate conversion circuitry. PR1 controls powerdown
for the DAC and the DAC sampling rate conversion circuitry.
PR2 powers down the mixer circuits (MIX1, MIX2, National
3D Sound, Mono Out, Line Out). PR3 powers down V
addition to all the same mixer circuits as PR2. PR4 powers
down the AC Link Digital Interface – see Figure 8 for signal
powerdown timing. PR5 disables internal clocks but leaves
the crystal oscillator and BIT_CLK running (needed for mini-
mum Primary mode powerdown dissipation in multi-codec
systems). PR6 and PR7 are not used.
After a subsection has undergone a powerdown cycle, the
appropriate status bit(s) in the Powerdown Control/Status
SR15:SR0
*BB80h
AC44h
1F40h
2B11h
3E80h
5622h
Common Sample Rates
10
= 1F40h. Below is a list of the
Sample Rate (Hz)
200308 Version 5 Revision 1
*48000
11025
16000
22050
44100
8000
FIGURE 8. AC Link Powerdown Timing
REF
in
Print Date/Time: 2009/07/15 15:26:52
23
designation. The first 24 bits (4Eh, 53h, 43h) represent the
three ASCII characters “NSC” which is National's Vendor ID
for Microsoft's Plug and Play. The last 8 bits are the two binary
coded decimal characters, 4, 6 and identify the codec to be
an LM4546A.
RESERVED REGISTERS
Do not write to reserved registers. In particular, do not write
to registers 24h, 5Ah, 74h and 7Ah. All registers not listed in
the LM4546A Register Map are reserved. Reserved Regis-
ters will return 0000h if read.
register (26h) must be polled to confirm readiness. In partic-
ular the startup time of the V
of the decoupling capacitors on pin 27 (3.3 µF, 0.1 µF in par-
allel is recommended) and this dependency is behind the
requirement for both PR2 and PR3 functionality in AC '97 Rev
2.
When the AC Link Digital Interface is powered down the
codec output signals SDATA_IN and BIT_CLK (Primary
mode) are cleared to zero and no control data can be passed
between controller and codec(s). This powerdown state can
be cleared in two ways: Cold Reset (RESET# = 0) or Warm
Reset (SYNC = 1, no BIT_CLK). Cold Reset sets all registers
back to their default values (including clearing PR4) whereas
Warm Reset only clears the PR4 bit and restarts the AC Link
Digital Interface leaving all register contents otherwise unaf-
fected. For Warm Reset (see Timing Diagrams), the SYNC
input is used asynchronously. The LM4546A codec allows the
AC Link digital interface powerdown state to be cleared im-
mediately so that its duration can be essentially as short as
T
with AC '97 Rev 2, Warm Reset should not be applied within
4 frame times of powerdown i.e. the AC Link powerdown state
should be allowed to last at least 82.8 µs.
SH
, the Warm Reset pulse width. However for conformance
REF
circuitry depends on the value
20030809
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