TP3040 NSC [National Semiconductor], TP3040 Datasheet - Page 7

• Manufacturer Part Number: TP3040
• Description: TP3040, TP3040A PCM Monolithic Filter
• Manufacturer: NSC [National Semiconductor]

Functional Description
The TP3040 TP3040A monolithic filter contains four main
sections Transmit Filter Receive Filter Receive Filter Pow-
er Amplifier and Frequency Divider Select Logic ( Figure 1 )
A brief description of the circuit operation for each section is
provided below
TRANSMIT FILTER
The input stage of the transmit filter is a CMOS operational
amplifier which provides an input resistance of greater than
10 M
consumption (less than 3 mW) high power supply rejection
and is capable of driving a 10 k
25 pF The inputs and output of the amplifier are accessible
for added flexibility Non-inverting mode inverting mode or
differential amplifier mode operation can be implemented
with external resistors It can also be connected to provide a
gain of up to 20 dB without degrading the overall filter per-
formance
The input stage is followed by a prefilter which is a two-pole
RC active low pass filter designed to attenuate high fre-
quency noise before the input signal enters the switched-ca-
pacitor high pass and low pass filters
A high pass filter is provided to reject 200 Hz or lower noise
which may exist in the signal path The low pass portion of
the switched-capacitor filter provides stopband attenuation
which exceeds the D3 and D4 specifications as well as the
CCITT G712 recommendations (Figure 3)
The output stage of the transmit filter the postfilter is also a
two-pole RC active low pass filter which attenuates clock
frequency noise by at least 40 dB The output of the trans-
mit filter is capable of driving a
into a 10 k
RECEIVE FILTER
The input stage of the receive filter is a prefilter which is
similar to the transmit prefilter The prefilter attenuates high
frequency noise that may be present on the receive input
signal A switched capacitor low pass filter follows the prefil-
ter to provide the necessary passband flatness stopband
rejection and sin x x gain correction A postfilter which is
similar to the transmit postfilter follows the low pass stage It
attenuates clock frequency noise and provides a low output
impedance capable of directly driving an electronic sub-
scriber-line-interface circuit (Figure 3)
RECEIVE FILTER POWER AMPLIFIERS
Two power amplifiers are also provided to interface to trans-
former coupled line circuits These two amplifiers are driven
by the output of the receive postfilter through gain setting
resistors R3 R4 ( Figure 2 ) The power amplifiers can be
deactivated when not required by connecting the power
amplifier input (pin 5) to the negative power supply V
This reduces the total filter power consumption by approxi-
mately 10 mW–20 mW depending on output signal ampli-
tude
a voltage gain of greater than 5 000 low power
load in parallel with up to 25 pF
g
load in parallel with up to
3 2V peak to peak signal
BB
7
Figure 2 shows the signal path interconnections between
POWER DOWN CONTROL
A power down mode is also provided A logic 1 power down
command applied on the PDN pin (pin 13) will reduce the
total filter power consumption to less than 1 mW Connect
PDN to GNDD for normal operation
FREQUENCY DIVIDER AND SELECT LOGIC CIRCUIT
This circuit divides the external clock frequency down to the
switching frequency of the low pass and high pass switched
capacitor filters The divider also contains a TTL-CMOS in-
terface circuit which converts the external TTL clock level to
the CMOS logic level required for the divider logic This in-
terface circuit can also be directly driven by CMOS logic A
frequency select circuit is provided to allow the filter to oper-
ate with 2 048 MHz 1 544 MHz or 1 536 MHz clock frequen-
cies By connecting the frequency select pin CLK0 (pin 14)
to V
tal ground selects 1 544 MHz and V
Applications Information
GAIN ADJUST
the TP3040 TP3040A and the TP3020 signal-channel CO-
DEC The transmit RC coupling components have been
chosen both for minimum passband droop and to present
the correct impedance to the CODEC during sampling
Optimum noise and distortion performance will be obtained
from the TP3040 TP3040A filter when operated with sys-
tem peak overload voltages of
and VF
overload voltage outside this range further gain or attenua-
tion may be required
BOARD LAYOUT
Care must be taken in PCB layout to minimize power supply
and ground noise Analog ground (GNDA) of each filter
should be connected to digital ground (GNDD) at a single
point which should be bypassed to both power supplies
Further power supply decoupling adjacent to each filter and
CODEC is recommended Ground loops should be avoided
both between GNDA and GNDD and between the GNDA
traces of adjacent filters and CODECs
CC
R
a 2 048 MHz clock input frequency is selected Digi-
O When interfacing to a PCM CODEC with a peak
g
2 5V to
BB
selects 1 536 MHz
g
3 2V at VF
x
O