TP3069V NSC [National Semiconductor], TP3069V Datasheet - Page 3

• Manufacturer Part Number: TP3069V
• Description: Enhanced' Serial Interface CMOS CODEC/Filter COMBO
• Manufacturer: NSC [National Semiconductor]

Functional Description
POWER-UP
When power is first applied power-on reset circuitry initializ-
es the COMBO
non-essential circuits are deactivated and the D
VPO
To power-up the device a logical low level or clock must be
applied to the MCLK
must be present Thus 2 power-down control modes are
available The first is to pull the MCLK
alternative is to hold both FS
low the device will power-down approximately 1 ms after
the last FS
FS
will remain in the high impedance state until the second FS
pulse
SYNCHRONOUS OPERATION
For synchronous operation the same master clock and bit
clock should be used for both the transmit and receive di-
rections In this mode a clock must be applied to MCLK
and the MCLK
control A low level on MCLK
and a high level powers down the device In either case
MCLK
transmit and receive circuits A bit clock must also be ap-
plied to BCLK
select the proper internal divider for a master clock of
1 536 MHz 1 544 MHz or 2 048 MHz For 1 544 MHz opera-
tion the device automatically compensates for the 193rd
clock pulse each frame
With a fixed level on the BCLK
selected as the bit clock for both the transmit and receive
directions Table I indicates the frequencies of operation
which can be selected depending on the state of BCLK
CLKSEL In this synchronous mode the bit clock BCLK
may be from 64 kHz to 2 048 MHz but must be synchro-
nous with MCLK
Each FS
data from the previous encode cycle is shifted out of the
enabled D
8-bit clock periods the TRI-STATE D
a high impedance state With an FS
latched via the D
BCLK
MCLK
ASYNCHRONOUS OPERATION
For asynchronous operation separate transmit and receive
clocks may be applied MCLK
2 048 MHz and need not be synchronous For best trans-
X
TABLE I Selection of Master Clock Frequencies
Clocked
0
1
BCLK
b
or FS
R
X
X R
and VPO
if running) FS
will be selected as the master clock for both the
X
R
X
R
X
pulse begins the encoding cycle and the PCM
output on the positive edge of BCLK
CLKSEL
pulse The TRI-STATE PCM data output D
or FS
X
R
TM
a
X
and the BCLK
R
PDN pin can be used as a power-down
and places it into a power-down state All
outputs are put in high impedance states
R
input on the negative edge of BCLK
R
pulse Power-up will occur on the first
X
PDN pin and FS
and FS
X
R
R
1 536 MHz or 1 544 MHz
and FS
R
R
PDN powers up the device
Frequency Selected
CLKSEL pin BLCK
must be synchronous with
X
CLKSEL can be used to
Master Clock
and MCLK
X
R
2 048 MHz
2 048 MHz
R
X
R
TP3069
output is returned to
pulse PCM data is
inputs continuously
and or FS
PDN pin high the
R
X
must be
R
X
X
VF
pulses
will be
After
X
R
(or
R
O
X
X
X
X
3
mission performance however MCLK
nous with MCLK
static logic levels to the MCLK
cally connect MCLK
Pin Description) For 1 544 MHz operation the device auto-
matically compensates for the 193rd clock pulse each
frame FS
chronous with MCLK
ing cycle and must be synchronous with BCLK
must be a clock the logic levels shown in Table I are not
valid in asynchronous mode BCLK
ate from 64 kHz to 2 048 MHz
SHORT FRAME SYNC OPERATION
The COMBO can utilize either a short frame sync pulse or a
long frame sync pulse Upon power initialization the device
assumes a short frame mode In this mode both frame sync
pulses FS
with timing relationships specified in Figure 2 With FS
during a falling edge of BCLK
BCLK
output the sign bit The following seven rising edges clock
out the remaining seven bits and the next falling edge dis-
ables the D
BCLK
of BCLK
edges latch in the seven remaining bits All devices may
utilize the short frame sync pulse in synchronous or asyn-
chronous operating mode
LONG FRAME SYNC OPERATION
To use the long frame mode both the frame sync pulses
FS
with timing relationships specified in Figure 3 Based on the
transmit frame sync FS
short or long frame sync pulses are being used For 64 kHz
operation the frame sync pulse must be kept low for a mini-
mum of 160 ns The D
with the rising edge of FS
whichever comes later and the first bit clocked out is the
sign bit The following seven BCLK
the remaining seven bits The D
falling BCLK
FS
receive frame sync pulse FS
D
BCLK
lize the long frame sync pulse in synchronous or asynchro-
nous mode
TRANSMIT SECTION
The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors
see Figure 4 The low noise and wide bandwidth allow gains
in excess of 20 dB across the audio passband to be real-
ized The op amp drives a unity-gain filter consisting of RC
active pre-filter followed by an eighth order switched-ca-
pacitor bandpass filter clocked at 256 kHz The output of
this filter directly drives the encoder sample-and-hold circuit
The A D is of companding type according to A-law coding
conventions A precision voltage reference is trimmed in
manufacturing to provide an input overload (t
nally 2 5V peak (see table of Transmission Characteristics)
R
X
X
to be latched in on the next eight falling edges of
and FS
going low whichever comes later A rising edge on the
X
R
R
(BCLK
enables the D
(BCLK
R
X
latches in the sign bit The following seven falling
X
X
R
starts each encoding cycle and must be syn-
X
and FS
output With FS
X
X
must be three or more bit clock periods long
edge following the eighth rising edge or by
in synchronous mode) All devices may uti-
in synchronous mode) the next falling edge
X
which is easily achieved by applying only
X
R
X
X
X
to all internal MCLK
and BCLK
must be one bit clock period long
TRI-STATE output buffer which will
TRI-STATE output buffer is enabled
X
the COMBO will sense whether
X
R
or the rising edge of BCLK
R
R
high during a falling edge of
X
will cause the PCM data at
PDN pin This will automati-
X
X
output is disabled by the
the next rising edge of
X
X
FS
and BCLK
rising edges clock out
R
R
should be synchro-
starts each decod-
R
functions (see
MAX
R
R
may oper-
) of nomi-
BCLK
X
high
X
R