MC68HC705BD3 FREESCALE [Freescale Semiconductor, Inc], MC68HC705BD3 Datasheet - Page 25

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MC68HC705BD3

Manufacturer Part Number
MC68HC705BD3
Description
High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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2.3.6
Port C and Port D are shared with PWM, M-Bus and SSP. The configuration registers at $0A and
$0B are used to configure those I/O pins. They are default to zero after power-on reset. Setting
these bits will set the corresponding pins to the corresponding functions, except PC6 and PC7.
For example, setting SCL and SDA bits of register $0B will configure Port D pins 1 and 0 as M-Bus
pins, regardless of DDR1 and DDR0 settings.
PC7 and PC6 are shared with both PWM and SSP. When HTTL and VTTL in $000B are set, PC7
and PC6 are configured as HTTL and VTTL outputs respectively, regardless of the status of
PWM15 and PWM14 in $000A. That is, HTTL and VTTL settings override PWM15 and PWM14
settings.
MC68HC05BD3
Configuration Register 1
Configuration Register 2
PWM15
Port C and D Configuration Registers
0
0
1
1
HTTL
0
1
0
1
Table 2-2 Configuration for PC6 and PC7
Address bit 7
Address bit 7
PIN DESCRIPTION AND I/O PORTS
$000A PWM15 PWM14 PWM13 PWM12 PWM11 PWM10 PWM9 PWM8 0000 0000
$000B
Result of PC7
PWM15
HTTL
HTTL
HTTL
PC7
VTTL
bit 6
bit 6
bit 5
bit 5
PWM14
0
0
1
1
bit 4
bit 4
bit 3
bit 3
VTTL
0
1
0
1
bit 2
bit 2
Result of PC6
bit 1
bit 1
SCL
PWM14
VTTL
VTTL
PC6
bit 0
bit 0
SDA
0000 0000
on reset
on reset
State
State
TPG
2-5
2

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