PIC18F248-E/L MICROCHIP [Microchip Technology], PIC18F248-E/L Datasheet - Page 272

• Manufacturer Part Number: PIC18F248-E/L
• Description: 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module
• Manufacturer: MICROCHIP [Microchip Technology]

REGISTER 24-9:
REGISTER 24-10: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh)
DS41159E-page 270
PIC18FXX8
bit 7-4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
bit 5-0
CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)
bit 7
Unimplemented: Read as ‘0’
EBTR3: Table Read Protection bit
1 = Block 3 (006000-007FFFh) not protected from table reads executed in other blocks
0 = Block 3 (006000-007FFFh) protected from table reads executed in other blocks
EBTR2: Table Read Protection bit
1 = Block 2 (004000-005FFFh) not protected from table reads executed in other blocks
0 = Block 2 (004000-005FFFh) protected from table reads executed in other blocks
EBTR1: Table Read Protection bit
1 = Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
0 = Block 1 (002000-003FFFh) protected from table reads executed in other blocks
EBTR0: Table Read Protection bit
1 = Block 0 (000200-001FFFh) not protected from table reads executed in other blocks
0 = Block 0 (000200-001FFFh) protected from table reads executed in other blocks
Legend:
R = Readable bit
-n = Value when device is unprogrammed
bit 7
Legend:
R = Readable bit
-n = Value when device is unprogrammed
Unimplemented: Read as ‘0’
EBTRB: Boot Block Table Read Protection bit
1 = Boot Block (000000-0001FFh) not protected from table reads executed in other blocks
0 = Boot Block (000000-0001FFh) protected from table reads executed in other blocks
Unimplemented: Read as ‘0’
Note 1: Unimplemented in PIC18FX48 devices; maintain this bit set.
U-0
—
U-0
—
EBTRB
R/P-1
U-0
—
P = Programmable bit
P = Programmable bit
U-0
—
U-0
—
(1)
(1)
U-0
—
U-0
—
EBTR3
R/P-1
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
U = Unimplemented bit, read as ‘0’
u = Unchanged from programmed state
U-0
—
(1)
EBTR2
R/P-1
U-0
—
© 2006 Microchip Technology Inc.
(1)
EBTR1
R/P-1
U-0
—
EBTR0
R/P-1
U-0
—
bit 0
bit 0