MC68HC908GT16_07 FREESCALE [Freescale Semiconductor, Inc], MC68HC908GT16_07 Datasheet - Page 97

• Manufacturer Part Number: MC68HC908GT16_07
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale Semiconductor
$0038
$0039
$003A
Addr.
Reset
OSCENINSTOP = 0,
STOP = 1
EXTCLKEN = 0
CMF = 1
CMON = 0
CMON = 1
CS = 0
CS = 1
ICGON = 0
ICGON = 1
ICGS = 0
ECGON = 0
ECGS = 0
IOFF = 1
EOFF = 1
N = written
TRIM = written
—
0, 1
0*, 1*
(0), (1)
us, uc, uw Register bit cannot be set, cleared, or written (respectively) in the given condition.
Condition
ICG DCO Stage Control
Register Name
ICG Divider Control
Register bit is unaffected by the given condition.
Register bit is forced clear or set (respectively) in the given condition.
Register bit is temporarily forced clear or set (respectively) in the given condition.
Register bit must be clear or set (respectively) for the given condition to occur.
Register (ICGDVR)
Register (ICGDSR)
ICG Trim Register
See page 100.
See page 100.
See page 100.
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Figure 7-11. ICG Module I/O Register Summary (Continued)
(ICGTR)
Table 7-4. ICG Module Register Bit Interaction Summary
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
(0)
(0)
—
—
—
—
—
us
us
—
—
0
0
0
0
0
0
DSTG7
TRIM7
(1)
(0)
(0)
—
—
—
—
—
—
Bit 7
1*
1*
0
0
0
0
0
0
R
1
0
(0)
(1)
(1)
(1)
(0)
(0)
us
us
—
—
—
0
0
0
1
0
0
= Unimplemented
DSTG6
TRIM6
R
6
0
0
Register Bit Results for Given Condition
(0)
(1)
uc
us
—
—
—
—
—
—
—
0
0
1
0
1
0
DSTG5
TRIM5
(0)
(1)
(1)
(1)
—
—
—
—
—
—
—
R
5
0
0
1
1
1
1
1
1
(0)
—
—
—
—
—
—
—
—
—
—
0*
0*
0
0
0
0
DSTG4
TRIM4
Unaffected by reset
R
R
4
0
0
(0)
(1)
(1)
—
—
—
—
—
—
—
—
0
0
1
1
1
1
= Reserved
DSTG3
TRIM3
DDIV3
U
R
3
0
(0)
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
$15
DSTG2
Input/Output (I/O) Registers
TRIM2
DDIV2
uw
uw
uw
uw
—
—
—
—
—
—
—
—
—
—
—
—
U
R
2
0
$80
U = Unaffected
uw
uw
uw
uw
—
—
—
—
—
—
—
—
—
—
—
—
DSTG1
TRIM1
DDIV1
U
R
1
0
uw
uw
uw
uw
uw
uw
uw
uw
—
—
—
—
—
—
—
—
—
DSTG0
TRIM0
DDIV0
Bit 0
U
R
0
uw
uw
uw
uw
uw
uw
uw
uw
—
—
—
—
—
—
—
—
—
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