DS8906N NSC [National Semiconductor], DS8906N Datasheet - Page 5

• Manufacturer Part Number: DS8906N
• Description: AM/FM Digital Phase-Locked Loop Synthesizer
• Manufacturer: NSC [National Semiconductor]

not be changed when ENABLE returns high
cepted as data and are shifted successively into the inter-
Applications Information
SERIAL DATA ENTRY INTO THE DS8906
Serial information entry into the DS8906 is enabled by a low
level on the ENABLE input One binary bit is then accepted
from the DATA input with each positive transition of the
CLOCK input The CLOCK input must be low for the speci-
fied time preceding and following the negative transition of
the ENABLE input
The first 2 bits accepted following the negative transition of
the ENABLE input are interpreted as address If these ad-
dress bits are not 1 1 no further information will be accept-
ed from the DATA inputs and the internal data latches will
If these first 2 bits are 1 1 then all succeeding bits are ac-
nal shift register as long as ENABLE remains low
Any data bits preceding the 20th to last bit will be shifted
out and are thus irrelevant Data bits are counted as any
bits following 2 valid (1 1) address bits with the ENABLE
low
When the ENABLE input returns high any further serial data
input is inhibited Upon this positive transition of the
ENABLE the data in the internal shift register is transferred
into the internal data latches
5
Note that until this time the states of the internal data latch-
es have remained unchanged
These data bits are interpreted as follows
DATA BIT POSITION
Note The actual divide code is N
Last
2nd to Last
3rd to Last
4th to Last
5th to Last
6th to Last
7th to Last
8th to Last
9th to Last
10th to Last
11th to Last
12th to Last
13th to Last
14th to Last
15th to Last
16th to Last
17th to Last
18th to Last
19th to Last
20th to Last
a
Bit 20 Output (Pin 2)
Bit 19 Output (Pin 1)
Bit 18 Output (FM AM) (Pin 20)
Bit 17 Output (Pin 19)
Bit 16 Output (Pin 18)
Bit 15 Output (Pin 17)
MSB of N (2
LSB of N
1 i e the number loaded plus 1
DATA INTERPRETATION
(2
(2
(2
(2
(2
(2
(2
(2
(2
(2
(2
(2
(2
13
12
11
10
9
8
7
6
5
4
3
2
1
0
)
)
)
)
)
)
)
)
)
)
)
)
)
)
d
N