LMH6554LE NSC [National Semiconductor], LMH6554LE Datasheet - Page 12

• Manufacturer Part Number: LMH6554LE
• Description: 2.8 GHz Ultra Linear Fully Differential Amplifier
• Manufacturer: NSC [National Semiconductor]

www.national.com
puts which is superimposed on the differential output signal.
The ratio of the change in output common mode voltage to
output differential voltage is commonly referred to as output
balance error. The output balance error response of the
LMH6554 over frequency is shown in the Typical Perfor-
mance Characteristics section.
To match the input impedance of the circuit in
specified source resistance, R
The equations governing R
operation are also provide in
with the source matching condition, must be solved iteratively
to achieve the desired gain with the proper input termination.
Component values for several common gain configuration in
a 50Ω environment are given in Table 1.
Table 1. Gain Component Values for 50Ω System
Single Supply Operation
Single 5V supply operation is possible: however, as dis-
cussed earlier, AC input coupling is recommended due to
input common mode limitations. An example of an AC cou-
pled, single supply, single-to-differential circuit is shown in
Figure
AC coupled irrespective of single-to-differential or differential-
differential configuration. For higher supply voltages DC cou-
pling of the inputs may be possible provided that the output
common mode DC level is set high enough so that the
amplifier's inputs and outputs are within their specified oper-
ation ranges.
Split Supply Operation
For optimum performance, split supply operation is recom-
mended using +2.5V and −2.5V supplies; however, operation
is possible on split supplies as low as +2.35V and −2.35V and
as high as +2.65V and −2.65V. Provided the total supply volt-
age does not exceed the 4.7V to 5.3V operating specification,
non-symmetric supply operation is also possible and in some
cases advantageous. For example, if a 5V DC coupled oper-
ation is required for low power dissipation but the amplifier
input common mode range prevents this operation, it is still
possible with split supplies of (V+) and (V-). Where (V+)-(V-)
FIGURE 3. AC Coupled for Single Supply Operation
Gain
12dB
0dB
6dB
3. Note that when AC coupling, both inputs need to be
200Ω
200Ω
200Ω
R
F
35.7Ω
191Ω
91Ω
IN
R
Figure
G
and A
S
, requries that R
2. These equations, along
V
for single-to-differential
76.8Ω
147Ω
62Ω
R
T
Figure 2
T
|| R
27.7Ω
30.3Ω
37.3Ω
R
IN
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M
= R
to a
S
.
12
= 5V and V+ and V- are selected to center the amplifier input
common mode range to suit the application.
Driving Analog To Digital
Converters
Analog-to-digital converters present challenging load condi-
tions. They typically have high impedance inputs with large
and often variable capacitive components.
LMH6554 driving an ultra-high-speed Gigasample ADC the
ADC10D1500. The LMH6554 common mode voltage is set
by the ADC10D1500. The circuit in
bandpass LC filter across the differential inputs of the AD-
C10D1500. The ADC10D1500 is a dual channel 10–bit ADC
with maximum sampling rate of 3 GSPS when operating in a
single channel mode and 1.5 GSPS in dual channel mode.
Figure 4
cy for the LMH6554 and ADC10D1500 combination circuit
with the ADC input signal level at −1dBFS. In order to properly
match the input impedance seen at the LMH6554 amplifier
inputs, R
ance. The amplifier is configured to provide a gain of 2 V/V in
single to differential mode. An external bandpass filter is in-
serted in series between the input signal source and the
amplifier to reduce harmonics and noise from the signal gen-
erator.
The amplifier and ADC should be located as close together
as possible. Both devices require that the filter components
be in close proximity to them. The amplifier needs to have
minimal parasitic loading on it's outputs and the ADC is sen-
sitive to high frequency noise that may couple in on its inputs.
Some high performance ADCs have an input stage that has
a bandwidth of several times its sample rate. The sampling
process results in all input signals presented to the input stage
mixing down into the first Nyquist zone (DC to Fs/2).
FIGURE 4. LMH6554/ADC10D1500 SFDR and SNR
shows the SFDR and SNR performance vs. frequen-
M
is chosen to match Z
Performance vs. Frequency
S
|| R
Figure 5
T
for proper input bal-
Figure 5
has a 2nd order
shows the
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