SX8723CWLTDT SEMTECH [Semtech Corporation], SX8723CWLTDT Datasheet

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... Digital outputs to bias Sensors Internal or external voltage reference Internal time base Low-power (250 uA for 16b @ 250 S/s) Fast I2C interface with external address option, no clock stretching required ORDERING INFORMATION SX8723CWLTDT - Available in tape and reel only - WEEE/RoHS compliant, Pb-Free and Halogen Free. SX8723C + - 1.2V ...

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ADVANCED COMMUNICATIONS & SENSING TABLE OF CONTENT Section E S LECTRICAL PECIFICATIONS 1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . ...

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ADVANCED COMMUNICATIONS & SENSING TABLE OF CONTENT Section 9.2.1 Address Set Externally . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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ADVANCED COMMUNICATIONS & SENSING ELECTRICAL SPECIFICATIONS 1 Absolute Maximum Ratings Note The Absolute Maximum Ratings, in table below, are stress ratings only. Functional operation of the device at conditions other than those indicated in the Operating Conditions sections of this ...

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ADVANCED COMMUNICATIONS & SENSING 2 Operating Conditions Unless otherwise specified: V REF,ADC PGA1&PGA2 off, offsets GDOff2 = GDOff3 = 0. Power operation: normal (IbAmpAdc[1:0] = IbAmpPga[1:0] = '01'). For resolution bits: OSR = 32 and N For ...

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ADVANCED COMMUNICATIONS & SENSING Table 3. Electrical Characteristics Parameter Input logic low Leakages currents Input leakage current VREF: Internal Bandgap Reference Absolute output voltage Variation over Temperature Total Output Noise 1. The device can be operated in either active or ...

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ADVANCED COMMUNICATIONS & SENSING Table 4. ZoomingADC Specifications Parameter ADC STATIC PERFORMANCES Resolution (No Missing Codes) Gain Error Offset Error Integral Non-Linearity Differential Non-Linearity Power Supply Rejection Ratio DC ADC DYNAMIC PERFORMANCES Conversion Time Throughput Rate (Continuous Mode) PGA Stabilization ...

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ADVANCED COMMUNICATIONS & SENSING (12) Conversion time is given by: T CONV (13) PGAs are reset after each writing operation to registers RegACCfg1-5, corresponding to change of configuration or input switching. The ADC should be started ...

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ADVANCED COMMUNICATIONS & SENSING 2.1 Timing Characteristics Table 5. General timings Parameter ADC INTERRUPT (READY) TIMING SPECIFICATIONS READY pulse width STARTUP TIMES Startup sequence time at POR Time to enable RC from Sleep after an I2C command (1) The READY ...

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ADVANCED COMMUNICATIONS & SENSING 2.1.2 I2C interface timings Table 6. Digital interface Parameter I2C TIMING SPECIFICATIONS Note 1 SCL clock frequency SCL timeout ( optional mode ) Note 2 SCL Low Pulsewidth SCL High Pulsewidth Start Condition Hold Time Data ...

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ADVANCED COMMUNICATIONS & SENSING 2.1.3 I2C timing Waveforms t PSU SCL t BF SDA Stop Figure 2. Definition of timing for F/S-mode on the I2C-bus. Revision 1.01 January 2011 © Semtech SCH ...

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ADVANCED COMMUNICATIONS & SENSING CIRCUIT DESCRIPTION 3 Pin Configuration 4 Marking Information nnnnn = Part Number 1 yyww = Date Code xxxxx = Semtech Lot Number xxxxx 1.Date codes and Lot numbers starting with the ‘E’ character are used for ...

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ADVANCED COMMUNICATIONS & SENSING 5 Pin Description Note The bottom pin is internally connected to VSS. It should also be connected to VSS on PCB to reduce noise and improve thermal behavior. Pin Name Type 1 AC4 Analog Input 2 ...

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ADVANCED COMMUNICATIONS & SENSING 6 General Description The SX8723C is a complete low-power acquisition path with programmable gain, acquisition speed and resolution. 6.1 Bloc diagram SX8723C V REF AC2 AC3 AC4 AC5 D0 (1) D1 D0: digital IO, Vref output ...

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ADVANCED COMMUNICATIONS & SENSING 6.3 GPIO The GPIO block is a multipurpose 2 bit input/output port. In addition to digital behavior, D0 and D1 pins can be programmed as analog pins in order to be used as output (reference voltage ...

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ADVANCED COMMUNICATIONS & SENSING 6.3.1 Optional Operating Mode: External Vref D0 and D1 are multi-functional pins with the following functions in different operating modes (see RegMode register for control settings): 0 D0/VREF OUT 1 RegMode[ Internal ...

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ADVANCED COMMUNICATIONS & SENSING 6.4 Charge Pump This block generates a supply voltage able to power the analog switch drive levels on the chip higher than V necessary voltage drops below 4.2V then the block should be activated. ...

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ADVANCED COMMUNICATIONS & SENSING 7 ZoomingADC 7.1 Overview The ZoomingADC is a complete and versatile low-power analog front-end interface typically intended for sensing applications. In the following text the ZoomingADC will be referred as ZADC. The key features of the ...

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ADVANCED COMMUNICATIONS & SENSING The core of the zooming section is made of three differential programmable amplifiers (PGA). After selection of an input and reference signals V and V IN stages Fine gain programming up to 1'000 ...

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ADVANCED COMMUNICATIONS & SENSING 7.1.3 PGA & ADC Enabling Depending on the application objectives, the user may enable or bypass each PGA stage. This is done according to the word Enable and the coding given in 7.2 ZoomingADC Registers The ...

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ADVANCED COMMUNICATIONS & SENSING (3) SetNelconv: (rw) sets the number of elementary conversions to 2 between elementary conversions (1,2,4,8). (4) SetOsr: (rw) sets the over-sampling rate (OSR elementary conversion to 2 (5) Continuous: (rw) setting this bit starts ...

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ADVANCED COMMUNICATIONS & SENSING Amux V INP (RegACCfg5[5:1]) Sign AC3 00x01 00x10 AC5 00x11 N.C. 10000 AC0(V SS 10001 AC1(V REF AC2 10010 AC3 10011 10100 AC4 10101 AC5 10110 N.C. 10111 N.C. Similarly, the reference voltage ...

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ADVANCED COMMUNICATIONS & SENSING 7.5 Second Stage Programmable Gain Amplifier (PGA2) The second PGA has a finer gain and offset tuning capability, as shown in PGA2 is given by: where GD and GD are respectively the gain and offset of ...

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ADVANCED COMMUNICATIONS & SENSING Pga3Gain bitfield (RegACCfg3[6:0]) ... 1000000 ... 1111111 The output of PGA3 is also the input of the ADC. Thus, similarly to PGA2, we find that the voltage entering the ADC is given by: where GD and ...

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ADVANCED COMMUNICATIONS & SENSING Finally, combining Equation by: IN where the total PGA gain is defined as: and the total PGA offset is: 7.6.1 PGA Ranges Figure 11 and Figure 12 illustrates the limits for the maximal ...

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ADVANCED COMMUNICATIONS & SENSING obtained only below these limits, as depicted in in Figure 12 if the supply voltage (V Max gain on first active PGA 10.0 5.0 2.5 Figure 11. Common mode input range on PGA for V Revision ...

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ADVANCED COMMUNICATIONS & SENSING Max gain First active PGA 10.0 5.0 2.5 V Figure 12. Common mode input range on PGA for V Max V 5.0 V 4.0 V 3.0 V 2.0 V 1.0 V 2.4 V Revision 1.01 January ...

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ADVANCED COMMUNICATIONS & SENSING 7.7 Analog-to-Digital Converter (ADC) The main performance characteristics of the ADC (resolution, conversion time, etc.) are determined by three programmable parameters. The setting of these parameters and the resulting performances are described later Over-sampling ...

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ADVANCED COMMUNICATIONS & SENSING 7.7.2 Over-Sampling Frequency (fs) The word SetFs[1:0] (see Table 14) is used to select the over-sampling frequency fs. The over-sampling frequency is derived from the 4MHz oscillator clock. 7.7.3 Over-Sampling Ratio (OSR) The over-sampling ratio (OSR) ...

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ADVANCED COMMUNICATIONS & SENSING SetOsr[2:0] (RegACCfg[4:2 already mentioned, N must be equal or greater than 2 to reduce internal amplifier offsets. ELCONV 7.7.5 Resolution The theoretical resolution of the ADC, without considering thermal noise, is ...

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ADVANCED COMMUNICATIONS & SENSING resolution is truncated to 16 bit by the output register size, it may make sense to set OSR and N in order to reduce the influence of the thermal noise in the PGA . Table 17. ...

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ADVANCED COMMUNICATIONS & SENSING Table 18. Normalized conversion time (Tconv x fs) vs. SetOsr and SetNelconv settings SetOsr bits OSR ‘100‘ ‘101‘ ‘110‘ ‘111‘ 1. Normalized to sampling period 1/fs 16.0 14.0 12.0 10.0 8.0 6.0 00 4.0 10 Figure ...

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ADVANCED COMMUNICATIONS & SENSING In "continuous-time" mode, the input signal is repeatedly converted into digital. After a conversion is finished, a new one is automatically initiated. The new value is then written in the result register, and the corresponding internal ...

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ADVANCED COMMUNICATIONS & SENSING where, from Equation 11 and Equation and: Table 19. Basic ADC Relationships (example for: VREF = 5V, OSR = 512 16bits) ADC Input Voltage % of Full Scale (FS) V IN,ADC +2.49505 V +0.5 ...

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ADVANCED COMMUNICATIONS & SENSING The equivalent LSB size at the input of the PGA chain is: Notice that the input voltage V IN,ADC to remain within the ADC input range. 7.7.9 Power Saving Modes During low-speed operation, the bias current ...

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ADVANCED COMMUNICATIONS & SENSING 8 Application hints 8.1 Power Reduction The ZoomingADC is particularly well suited for low-power applications. When very low power consumption is of primary concern, such as in battery operated systems, several parameters can be used to ...

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ADVANCED COMMUNICATIONS & SENSING 8.2 Gain Configuration Flow The diagram below shows the flow to set the gain of your configuration: Set gain Gain < Yes Enable PGA3 Set PGA 3 gain GAIN = PGA3 Revision 1.01 January ...

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ADVANCED COMMUNICATIONS & SENSING 9 I2C Interface The I2C interface gives access to the chip registers. It complies with the I2C protocol specifications, restricted to the slave side of the communication. The device uses a Generic Fast-Mode (400 KHz) I2C ...

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ADVANCED COMMUNICATIONS & SENSING 9.2.1 Address Set Externally Bit: Slave address: Address bit[0] set to 1 Address bit[1] set to 0 Figure 20. Example of I2C address set by external resistors The GPIO are set as ouput low at startup, ...

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ADVANCED COMMUNICATIONS & SENSING 9.4 I2C Register Access 9.4.1 Writing a Register SDA 9.4.2 Reading in a Registe DEVICE R T ADDRESS SDA 9.4.3 Writing in Several Consecutive Registers ...

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ADVANCED COMMUNICATIONS & SENSING 9.4.4 Reading from Several Consecutive Registers DEVICE T ADDRESS SDA Figure 25. I2C timing diagram for multiple reading from a register Revision 1.01 January 2011 © ...

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ADVANCED COMMUNICATIONS & SENSING 10 Register Memory Map and Description 10.1 Register Map Table 22 below describes the register/memory map that can be accessed through the I2C interface. It indicates the register name, register address and the register contents. Table ...

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ADVANCED COMMUNICATIONS & SENSING 10.2.1 RC Register Table 23. RegRCen[0x30] Bit Bit Name 7 RCEn 10.2.2 GPIO Registers Table 24. RegOut[0x40] Bit Bit Name 7 D1Dir 4 D0Dir 3 D1Out 0 D0Out Table 25. ...

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ADVANCED COMMUNICATIONS & SENSING Table 27. RegExtAdd[0x43] Bit Bit Name 7:0 ExternalRd 10.2.3 ZADC Registers Table 28. RegACOutLsb[0x50] Bit Name 7:0 Out[7:0] Table 29. RegACOutMsb[0x51] Bit Name 7:0 Out[15:8] Table 30. RegACCfg0[0x52] Bit Name 7 Start 6:5 SetNelconv 4:2 SetOsr ...

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ADVANCED COMMUNICATIONS & SENSING Table 32. RegACCfg2[0x54] Bit Name 7:6 SetFs 5:4 Pga2Gain 3:0 Pga2Offset Table 33. RegACCfg3[0x55] Bit Name 7 Pga1Gain 6:0 Pga3Gain Table 34. RegACCfg4[0x56] Bit Name 7 - 6:0 Pga3Offset Table 35. RegACCfg5[0x57] Bit Name 7 Busy ...

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ADVANCED COMMUNICATIONS & SENSING 10.2.4 Mode Registers Table 36. RegMode[0x70] Bit Name 5:4 Chopper 3 MultForceOn 2 MultForceOff 1 VrefD0Out 0 VrefD1In (1) The chop control is to allow chopping of the internal bandgap reference. This ...

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ADVANCED COMMUNICATIONS & SENSING 11 Typical Performances Note The graphs and tables provided following this note are statistical summary based on limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested ...

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ADVANCED COMMUNICATIONS & SENSING 11.1.1 Switched Capacitor Principle Basically, a switched capacitor is a way to emulate a resistor by using a capacitor. The capacitors are much easier to realize on CMOS technologies and they show a very good matching ...

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ADVANCED COMMUNICATIONS & SENSING show short voltage spikes at the frequency fs, but these will not influence the measurement. Whereas if the bandwidth of the node is lower, no spikes will arise, but a small offset can be generated by ...

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ADVANCED COMMUNICATIONS & SENSING 1.2 1 0.8 0.6 0.4 0 0.5 1 1.5 2 Normalized Frequency - f x (OSR / fs) [-] 1.2 1 0.8 0.6 0.4 0 0.5 1 1.5 2 Normalized Frequency - ...

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ADVANCED COMMUNICATIONS & SENSING 11.3.1.1 Gain PGAs disabled; OSR=1024 ; Nelconv=8 ; fs=250kHz; Resolution=16bits. BATT REF BATT 10 INL Gain 1 @ -40° -10 ...

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ADVANCED COMMUNICATIONS & SENSING 10 INL Gain 10 @ 85° -10 -0.2 -0.15 -0.1 -0. [V] IN Figure 35. INL 85°C 11.3.1.3 Gain 100 V = ...

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ADVANCED COMMUNICATIONS & SENSING 11.3.1.4 Gain 1000 V = ADC, PGA3, PGA2, PGA1 enabled; GD BATT REF BATT; fs=250KHz; Resolution=16bits. 200 INL Gain 1000 @ -40°C 150 100 50 0 -50 -100 -150 -200 -0.002 -0.0015 -0.001 ...

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ADVANCED COMMUNICATIONS & SENSING 11.3.2 Differential Non-Linearity The differential non-linearity is generated by the ADC. The PGA does not add differential non-linearity. the differential non-linearity. Figure 45. Differential Non-Linearity of the ADC Converter 11.4 Noise Ideally, a constant input voltage ...

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ADVANCED COMMUNICATIONS & SENSING VSS VREF AC2 AC3 Analog AC4 Inputs AC5 N.C. N.C. V REFN,WB VBATT Reference VSS VREF Inputs VSS and V are the output rms noise figures respectively. V ...

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ADVANCED COMMUNICATIONS & SENSING As shown in Equation 28, noise can be reduced by increasing OSR and N but reduces noise). Table 39. PGA Noise Measurement (n = 16bits, OSR = 512, N Parameter Output RMS noise(uV) Figure 47 shows ...

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ADVANCED COMMUNICATIONS & SENSING 11.5 Gain Error and Offset Error Gain error is defined as the amount of deviation between the ideal transfer function (theoretical 33) and the measured transfer function (with the offset error removed). The actual gain of ...

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ADVANCED COMMUNICATIONS & SENSING 11.6 Power Consumption Figure 51 plots the variation of current consumption with supply voltage V 3 PGA stages and the ADC (see Table 40, page V > 4.2V. BATT 1'100 1'000 900 800 700 600 500 ...

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ADVANCED COMMUNICATIONS & SENSING As shown in Figure 52, if lower sampling frequency is used, the current consumption can be lowered by reducing the bias currents of the PGAs and the ADC with registers IbAmpPga and IbAmpAdc. (In '00' for ...

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ADVANCED COMMUNICATIONS & SENSING Current consumption vs. temperature is depicted in 1300 1200 1100 1000 900 800 700 600 -40 Figure 53. Current Consumption vs Temperature and Supply Voltage Table 40. Typical Current Distribution in Acquisition Chain ( ...

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ADVANCED COMMUNICATIONS & SENSING FAMILY OVERVIEW This chapter gives an overview of similar devices based on the ZoomingADC but with different features or packages. Each part is described in it’s own datasheet. 12 Comparizon table Table 41. Family comparizon table ...

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ADVANCED COMMUNICATIONS & SENSING 13 Comparizon by package pinout I2C versions AC4 1 AC5 2 VBATT 3 SX8723C (Top view) VSS 4 READY AC3 1 AC6 2 SX8724C (Top view) AC7 3 AC4 4 ...

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ADVANCED COMMUNICATIONS & SENSING MECHANICAL 14 PCB Layout Considerations PCB layout considerations to be taken when using the SX8723C are relatively simple to get the highest performances out of the ZoomingADC. The most important to achieve good performances out the ...

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ADVANCED COMMUNICATIONS & SENSING 16 Package Outline Drawing: 4x4MLPD-W12-EP1 ...

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ADVANCED COMMUNICATIONS & SENSING 17 Land Pattern Drawing: 4x4MLPD-W12-EP1 R ( NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. 2. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S ...

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ADVANCED COMMUNICATIONS & SENSING 18 Tape and Reel Specification MLP/QFN (0.70mm - 1.00mm package thickness) Single Sprocket holes Tolerances for Ao & Bo are +/- 0.20mm Tolerances for Ko is +/- 0.10mm Tolerance for Pocket Pitch is +/- 0.10mm Tolerance ...

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ADVANCED COMMUNICATIONS & SENSING © Semtech 2010 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation ...