XTR111_07 BURR-BROWN [Burr-Brown Corporation], XTR111_07 Datasheet - Page 19

• Manufacturer Part Number: XTR111_07
• Description: Precision Voltage-to-Current Converter/Transmitter
• Manufacturer: BURR-BROWN [Burr-Brown Corporation]

PACKAGE AND HEAT SINKING
The dominant portion of power dissipation for the current
output is in the external FET.
The XTR111 only generates heat from the supply voltage
with the quiescent current, the internal signal current that
is 1/10 of the output current and the current and internal
voltage drop of the regulator.
The exposed thermal pad on the bottom of the XTR111
package allows excellent heat dissipation of the device
into the printed circuit board (PCB).
THERMAL PAD
The thermal pad must be connected to the same voltage
potential as the device GND pin.
Packages with an exposed thermal pad are specifically
designed to provide excellent power dissipation, but board
layout greatly influences overall heat dissipation. The
thermal resistance from junction-to-ambient (T
specified for the packages with the exposed thermal pad
soldered to a normalized PCB, as described in Technical
Brief
Package. See also EIA/JEDEC Specifications JESD51-0
to 7, QFN/SON PCB Attachment (SLUA271), and Quad
Flatpack No-Lead Logic Packages (SCBA017). These
documents are available for download at www.ti.com.
NOTE: All thermal models have an accuracy 20%.
www.ti.com
SLMA002,
Figure 15. Voltage Regulator Current Boost Using a Standard NPN Transistor
3V
(a)
NPN
PowerPAD
Q2
C
470nF
1kΩ
2
R
3
Thermally-Enhanced
REGF
REGS
JA
) is
NOTE: (1) Resistor R
Component population, layout of traces, layers, and air
flow strongly influence heat dissipation. Worst-case load
conditions should be tested in the real environment to
ensure proper thermal conditions. Minimize thermal stress
for proper long-term operation with a junction temperature
well below +125°C.
LAYOUT GUIDELINES
The leadframe die pad should be soldered to a thermal pad
on the PCB. A mechanical data sheet showing an example
layout is attached at the end of this data sheet.
Refinements to this layout may be required based on
assembly process requirements. Mechanical drawings
located at the end of this data sheet list the physical
dimensions for the package and pad. The five holes in the
landing pattern are optional, and are intended for use with
thermal vias that connect the leadframe die pad to the
heatsink area on the PCB.
Soldering the exposed pad significantly improves
board-level reliability during temperature cycling, key
push, package shear, and similar board-level tests. Even
with applications that have low-power dissipation, the
exposed pad must be soldered to the PCB to provide
structural integrity and long-term reliability.
6V
(b)
NPN
Q2
from overcurrent in fault conditions.
C
470nF
100Ω
10kΩ
R
1kΩ
R
R
2
4
(1)
3
1
4
can be calculated to protect Q
+24V
R
10kΩ
2
REGF
REGS
SBOS375 − NOVEMBER 2006
2
XTR111
19